Anonymous788 / YOLO_BlockCir
☆31Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for YOLO_BlockCir
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆24Updated 6 years ago
- The second place winner for DAC-SDC 2020☆96Updated 2 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆110Updated 3 years ago
- ☆69Updated 4 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆47Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆35Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆19Updated 5 years ago
- ☆35Updated 5 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 5 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆106Updated 7 years ago
- HLS implemented systolic array structure☆40Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆88Updated 5 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆36Updated 3 years ago
- hls code zynq 7020 pynq z2 CNN☆77Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- This is an open CNN accelerator for everyone to use☆14Updated 5 years ago
- The CNN based on the Xilinx Vivado HLS☆35Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆87Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆119Updated 5 years ago
- Codes to implement MobileNet V2 in a FPGA☆23Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆51Updated 2 years ago
- ☆43Updated 6 years ago
- DAC System Design Contest 2020☆29Updated 4 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆20Updated 5 years ago
- 中文:☆91Updated 4 years ago