Alternatives and similar repositories for Free-TPU

Users that are interested in Free-TPU are comparing it to the libraries listed below

• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆220Updated last year
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆150Updated 5 years ago
• LeiWang1999 / ZYNQ-NVDLA
  NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
  ☆335Updated last year
• Xilinx / QNN-MO-PYNQ
  ☆246Updated 4 years ago
• Xilinx / CHaiDNN
  HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
  ☆324Updated 5 years ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆418Updated 5 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆145Updated last year
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆271Updated 5 years ago
• changwoolee / lenet5_hls
  FPGA Accelerator for CNN using Vivado HLS
  ☆316Updated 3 years ago
• OpenDLA / OpenDLA
  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
  ☆143Updated 7 years ago
• Xilinx / SDSoC-Tutorials
  SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials
  ☆153Updated 5 years ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆464Updated 6 years ago
• JunningWu / Learning-NVDLA-Notes
  NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…
  ☆226Updated 6 years ago
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆157Updated 7 years ago
• mtmd / FPGA_Based_CNN
  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
  ☆181Updated 8 years ago
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆106Updated 6 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆104Updated 7 years ago
• HWAC-DL / hwac_object_tracker
  FPGA accelerated TinyYOLO v2 object detection neural network
  ☆72Updated 6 years ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆212Updated 6 years ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆126Updated 5 months ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆340Updated 3 months ago
• Xilinx / PYNQ-ComputerVision
  Computer Vision Overlays on Pynq
  ☆178Updated 5 years ago
• lulinchen / cnn_open
  A hardware implementation of CNN, written by Verilog and synthesized on FPGA
  ☆231Updated 6 years ago
• xjtuiair-cag / XJTU-Tripler
  XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
  ☆180Updated last year
• cornell-zhang / bnn-fpga
  Binarized Convolutional Neural Networks on Software-Programmable FPGAs
  ☆303Updated 4 years ago
• xupsh / pp4fpgas-cn-hls
  HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
  ☆236Updated 4 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆118Updated 3 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆180Updated 7 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆179Updated last year
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆195Updated last week