cxdzyq1110 / NPU_on_FPGALinks
在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。
☆247Updated 6 years ago
Alternatives and similar repositories for NPU_on_FPGA
Users that are interested in NPU_on_FPGA are comparing it to the libraries listed below
Sorting:
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆338Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆180Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆180Updated 7 months ago
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- CPU Design Based on RISCV ISA☆113Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆155Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆211Updated 2 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆235Updated 6 years ago
- IC implementation of Systolic Array for TPU☆251Updated 8 months ago
- FPGA☆155Updated 11 months ago
- AXI协议规范中文翻译版☆152Updated 2 years ago
- AMBA bus lecture material☆441Updated 5 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆95Updated 2 weeks ago
- Deep Learning Accelerator (Convolution Neural Networks)☆186Updated 7 years ago
- some interesting demos for starters☆81Updated 2 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆153Updated 2 years ago
- PYNQ学习资料☆163Updated 5 years ago
- 一个开源的FPGA神经网络加速器。☆166Updated last year
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆113Updated last year
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆236Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- ☆146Updated this week
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆140Updated 5 years ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆562Updated 7 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆151Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆154Updated last year
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆336Updated 2 years ago
- ☆135Updated 10 years ago