Alternatives and similar repositories for NPU_on_FPGA:

Users that are interested in NPU_on_FPGA are comparing it to the libraries listed below

• LeiWang1999 / ZYNQ-NVDLA
  NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
  ☆330Updated last year
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆172Updated last year
• lulinchen / cnn_open
  A hardware implementation of CNN, written by Verilog and synthesized on FPGA
  ☆226Updated 6 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆196Updated last year
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆146Updated last year
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆143Updated 5 years ago
• MasLiang / CNN-On-FPGA
  FPGA
  ☆151Updated 8 months ago
• xupsh / pp4fpgas-cn-hls
  HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
  ☆236Updated 3 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆412Updated 5 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆177Updated 7 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆204Updated 5 months ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• XueTianyu24 / cnn_accelerator
  【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
  ☆138Updated last year
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆68Updated last week
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆156Updated 4 months ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆141Updated 2 years ago
• Yu-Zhewen / Tiny_YOLO_v3_ZYNQ
  Implement Tiny YOLO v3 on ZYNQ
  ☆282Updated 2 years ago
• louisliuwei / PynqDocs
  PYNQ学习资料
  ☆162Updated 5 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆185Updated last year
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆209Updated 7 years ago
• xddcore / OpenNNA
  一个开源的FPGA神经网络加速器。
  ☆149Updated last year
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆141Updated last month
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆97Updated 9 months ago
• ljgibbslf / SM3_core
  ☆141Updated 4 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆147Updated 5 years ago
• QShen3 / CNN-FPGA
  使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
  ☆533Updated 6 years ago
• suisuisi / FPGAandCNN
  基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
  ☆308Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆194Updated last year
• YutongChenVictor / Fpga-accelerator-demos
  some interesting demos for starters
  ☆73Updated 2 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆99Updated 6 years ago