nachiket / papaa-openclView external linksLinks
OpenCL Labs for PAPAA Summer School 2016 Edition
☆46Jul 24, 2017Updated 8 years ago
Alternatives and similar repositories for papaa-opencl
Users that are interested in papaa-opencl are comparing it to the libraries listed below
Sorting:
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Feb 12, 2018Updated 8 years ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,367Feb 14, 2022Updated 4 years ago
- Python on Zynq FPGA for Convolutional Neural Networks☆624May 15, 2018Updated 7 years ago
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆785Dec 10, 2019Updated 6 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆187Jan 28, 2017Updated 9 years ago
- Support for zScale on Spartan6 FPGAs☆15Aug 3, 2015Updated 10 years ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆769May 26, 2017Updated 8 years ago
- ☆10Feb 17, 2017Updated 8 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- CNN accelerator☆29Jun 11, 2017Updated 8 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆116Jun 24, 2017Updated 8 years ago
- FPGA Accelerator for CNN using Vivado HLS☆331Oct 25, 2021Updated 4 years ago
- ☆119Dec 20, 2017Updated 8 years ago
- DyRACT Open Source Repository☆16May 4, 2016Updated 9 years ago
- Winograd-based convolution implementation in OpenCL☆28Jan 22, 2017Updated 9 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 7 years ago
- ECCV2018☆18Aug 9, 2018Updated 7 years ago
- Quantized Neural Networks (QNNs) on PYNQ☆703Jan 4, 2022Updated 4 years ago
- 中文版 Parallel Programming for FPGAs☆761Aug 21, 2024Updated last year
- GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA☆181Jul 20, 2019Updated 6 years ago
- FPGA☆159Jun 29, 2024Updated last year
- Binary Neural Network on IceStick FPGA.☆54Jul 11, 2018Updated 7 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- ☆24Nov 10, 2020Updated 5 years ago
- ☆28Feb 21, 2018Updated 7 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Dec 11, 2020Updated 5 years ago
- ☆26Dec 1, 2016Updated 9 years ago
- Hand written number classification done in hardware (De1-SoC board) using neural networks☆25Mar 21, 2018Updated 7 years ago
- Various experiments on the [Fashion-MNIST](https://github.com/zalandoresearch/fashion-mnist) dataset from Zalando☆31Sep 28, 2017Updated 8 years ago
- matlab code for 2017 Detail-Enhanced Multi-Scale Exposure Fusion☆28Nov 22, 2017Updated 8 years ago
- Community maintained hardware plugin for vLLM on AWS Neuron☆21Updated this week
- OpenCL Demos for Xilinx FPGAs☆31Dec 7, 2015Updated 10 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Nov 7, 2019Updated 6 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- ☆35Dec 2, 2016Updated 9 years ago
- A code for converting and testing Tensorflow models for AI Challenge☆29Jul 16, 2020Updated 5 years ago
- Code for Class-Splitting Generative Adversarial Networks☆32Oct 3, 2017Updated 8 years ago
- ☆32Apr 21, 2019Updated 6 years ago