xddcore / OpenNNALinks
一个开源的FPGA神经网络加速器。
☆166Updated last year
Alternatives and similar repositories for OpenNNA
Users that are interested in OpenNNA are comparing it to the libraries listed below
Sorting:
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆153Updated 2 years ago
- some interesting demos for starters☆81Updated 2 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆113Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆180Updated 7 months ago
- FPGA project☆222Updated 3 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆79Updated 4 years ago
- ☆240Updated last year
- FPGA☆155Updated 11 months ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆76Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆180Updated last year
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆54Updated 3 months ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆61Updated last year
- Implement Tiny YOLO v3 on ZYNQ☆294Updated 2 months ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆336Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆176Updated last year
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆247Updated 6 years ago
- Convolutional Neural Network RTL-level Design☆58Updated 3 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆149Updated 4 years ago
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆140Updated 5 years ago
- ☆53Updated 2 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆95Updated 2 weeks ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆235Updated 6 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆25Updated 2 years ago
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆512Updated 4 years ago
- 2023集创赛紫光同创杯一等奖项目☆117Updated last year
- 代码在这个库里 Code is here☆52Updated 7 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆211Updated 2 years ago