Alternatives and similar repositories for pld2022:

Users that are interested in pld2022 are comparing it to the libraries listed below

• icgrp / prflow_nested_dfx
  Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
  ☆13Updated last year
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 3 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 6 months ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆34Updated 2 weeks ago
• icgrp / hipr
  ☆15Updated 2 years ago
• lana555 / dynamatic
  ☆86Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆29Updated this week
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆71Updated 5 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆24Updated 7 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆49Updated last month
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• Xilinx / merlin-compiler
  ☆57Updated last year
• sfu-arch / muir
  ☆24Updated 4 years ago
• pku-liang / ksim
  ☆40Updated 3 months ago
• UIUC-ChenLab / Nimblock
  ☆13Updated last year
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆29Updated 6 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆90Updated 6 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated last month
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆51Updated 5 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆67Updated this week
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆121Updated 5 years ago
• tancheng / CGRA-Bench
  ☆15Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• pnnl / soda-opt
  ☆44Updated last month