UCLA-VAST / TAPA-CSLinks
☆13Updated last year
Alternatives and similar repositories for TAPA-CS
Users that are interested in TAPA-CS are comparing it to the libraries listed below
Sorting:
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated 7 months ago
- ☆72Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆16Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆61Updated 9 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆74Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A research shell for Alveo V80☆21Updated 3 weeks ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated 3 weeks ago
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- ACM TODAES Best Paper Award, 2022☆32Updated 2 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 4 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆46Updated this week
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆46Updated 5 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- An HBM FPGA based SpMV Accelerator☆17Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- ☆10Updated 2 years ago
- ☆13Updated 2 years ago
- ☆42Updated last year
- ☆29Updated 4 years ago