UCLA-VAST / TAPA-CSLinks
☆12Updated last year
Alternatives and similar repositories for TAPA-CS
Users that are interested in TAPA-CS are comparing it to the libraries listed below
Sorting:
- ☆72Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- ☆16Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆25Updated 4 months ago
- ☆29Updated 5 months ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆53Updated last year
- ☆40Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆40Updated this week
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆44Updated last month
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- ☆10Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 4 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆21Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆69Updated 5 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆14Updated last year
- ACM TODAES Best Paper Award, 2022☆28Updated last year
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆14Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 6 months ago
- ☆58Updated 5 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago