cornell-zhang / FracBNNLinks
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
☆94Updated 3 years ago
Alternatives and similar repositories for FracBNN
Users that are interested in FracBNN are comparing it to the libraries listed below
Sorting:
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- ☆71Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- Open-source of MSD framework☆16Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆44Updated 11 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- ☆28Updated 4 months ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- ☆72Updated 2 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- ☆35Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆147Updated 3 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago
- ☆11Updated last year
- ☆34Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- ☆41Updated last year
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆58Updated last week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆150Updated this week
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- ☆18Updated 2 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month