AlexMontgomerie / samoLinks
SAMO: Streaming Architecture Mapping Optimisation
☆34Updated 2 years ago
Alternatives and similar repositories for samo
Users that are interested in samo are comparing it to the libraries listed below
Sorting:
- ☆65Updated 5 years ago
- ☆72Updated 2 years ago
- NeuraLUT-Assemble☆47Updated 5 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆22Updated 3 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆55Updated last year
- ☆35Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- ☆71Updated 5 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- An LSTM template and a few examples using Vivado HLS☆47Updated last year
- ☆30Updated 6 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- ☆32Updated 10 months ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Updated 6 years ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆29Updated last year
- HLS implemented systolic array structure☆41Updated 8 years ago
- ☆32Updated last year
- Approximate layers - TensorFlow extension☆26Updated 9 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- ☆45Updated this week
- ☆19Updated 4 years ago
- ☆19Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Updated 4 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago