AlexMontgomerie / samoLinks
SAMO: Streaming Architecture Mapping Optimisation
☆34Updated 2 years ago
Alternatives and similar repositories for samo
Users that are interested in samo are comparing it to the libraries listed below
Sorting:
- ☆72Updated 2 years ago
- ☆63Updated 5 years ago
- NeuraLUT-Assemble☆43Updated 3 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- ☆71Updated 5 years ago
- ☆35Updated 6 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆22Updated last year
- ☆22Updated 3 years ago
- ☆30Updated 6 years ago
- ☆31Updated 8 months ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 6 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Train and deploy LUT-based neural networks on FPGAs☆102Updated last year
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆60Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆54Updated last year
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆16Updated 11 months ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆146Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆25Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆28Updated last year
- ☆38Updated 8 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year