An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
☆61Aug 1, 2025Updated 7 months ago
Alternatives and similar repositories for Stream-HLS
Users that are interested in Stream-HLS are comparing it to the libraries listed below
Sorting:
- ☆62Mar 24, 2025Updated 11 months ago
- Large-scale medical image processing and reconstruction toolbox☆18Feb 13, 2024Updated 2 years ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆13May 22, 2025Updated 10 months ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆361Mar 13, 2026Updated last week
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆185Mar 8, 2026Updated last week
- ☆14May 23, 2024Updated last year
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆16Dec 29, 2024Updated last year
- A scalable High-Level Synthesis framework on MLIR☆291May 15, 2024Updated last year
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆24May 23, 2024Updated last year
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆33Nov 12, 2024Updated last year
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆22Oct 31, 2024Updated last year
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆20Dec 10, 2024Updated last year
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆171Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆168Mar 12, 2026Updated last week
- Vivado HLS study notes, courses, documents.☆12Dec 7, 2019Updated 6 years ago
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆60Mar 8, 2026Updated 2 weeks ago
- ☆14Oct 14, 2025Updated 5 months ago
- ☆17Aug 29, 2024Updated last year
- ☆128Updated this week
- ☆17Mar 26, 2025Updated 11 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆50Updated this week
- [FCCM 2023] PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs☆14Jun 26, 2025Updated 8 months ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- A unified programming framework for high and portable performance across FPGAs and GPUs☆11Mar 23, 2025Updated 11 months ago
- Fork of LLVM to support AMD AIEngine processors☆188Updated this week
- ☆13Oct 26, 2023Updated 2 years ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- ☆40Jun 30, 2025Updated 8 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆240Dec 8, 2022Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Dec 19, 2025Updated 3 months ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 4 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆36Mar 12, 2026Updated last week
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Nov 15, 2022Updated 3 years ago
- EQueue Dialect☆42Feb 3, 2022Updated 4 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Oct 23, 2018Updated 7 years ago
- An MLIR-based toolchain for AMD AI Engine-enabled devices.☆593Updated this week
- Open-source AI acceleration on FPGA: from ONNX to RTL☆49Updated this week
- A hardware synthesis framework with multi-level paradigm☆44Jan 10, 2025Updated last year