UCLA-VAST / Stream-HLSLinks
An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
☆47Updated last month
Alternatives and similar repositories for Stream-HLS
Users that are interested in Stream-HLS are comparing it to the libraries listed below
Sorting:
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- ☆58Updated 5 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- An Open-Source Tool for CGRA Accelerators☆72Updated last week
- ☆49Updated 2 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆137Updated 3 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆63Updated 6 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆155Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆223Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- An integrated CGRA design framework☆90Updated 6 months ago
- A hardware synthesis framework with multi-level paradigm☆40Updated 8 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- An Open-Source Tool for CGRA Accelerators☆24Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- ☆60Updated this week
- ☆87Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆157Updated 3 weeks ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated last month
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- CGRA framework with vectorization support.☆35Updated last week
- ☆31Updated 10 months ago
- A scalable High-Level Synthesis framework on MLIR☆274Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆63Updated 4 months ago
- ☆13Updated 2 years ago