cornell-brg / pymtl-tut-hls

Related projects ⓘ

Alternatives and complementary repositories for pymtl-tut-hls

• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• UIUC-ChenLab / rip
  ☆17Updated 6 years ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆15Updated 5 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆26Updated 7 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆44Updated 8 years ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆19Updated 7 months ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 3 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆48Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆47Updated 4 years ago
• icgrp / hipr
  ☆11Updated last year
• xupgit / compute_acceleration
  ☆12Updated 4 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆30Updated 3 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆49Updated 4 years ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 3 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆36Updated 2 months ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 2 months ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆38Updated 4 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆27Updated last year
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆27Updated last year
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆14Updated 10 years ago
• cornell-brg / pymtl-tutorial-isca2019
  Code for PyMTL Tutorial @ ISCA 2019
  ☆11Updated 5 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆37Updated 2 years ago