☆15Jul 7, 2020Updated 5 years ago
Alternatives and similar repositories for dnn-accelerator
Users that are interested in dnn-accelerator are comparing it to the libraries listed below
Sorting:
- Tool for optimize CNN blocking☆95Mar 22, 2020Updated 5 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆12May 3, 2024Updated last year
- ☆29Nov 5, 2021Updated 4 years ago
- A reference implementation of the Mind Mappings Framework.☆30Dec 2, 2021Updated 4 years ago
- ☆29Jun 10, 2019Updated 6 years ago
- ☆13Jun 20, 2023Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆62Dec 3, 2021Updated 4 years ago
- ☆32Aug 21, 2021Updated 4 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Jan 3, 2022Updated 4 years ago
- Zeonica is a simulator for CGRA and Wafer-Scale Accelerators.☆18Updated this week
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- ☆19Mar 21, 2023Updated 2 years ago
- ☆72Feb 16, 2023Updated 3 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- ☆44Jun 30, 2024Updated last year
- The Chronos FPGA Framework to accelerate ordered applications☆22May 20, 2020Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 4 years ago
- ☆28Feb 26, 2023Updated 3 years ago
- ☆19Aug 9, 2022Updated 3 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 3 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Nov 7, 2019Updated 6 years ago
- HLS branch of Halide☆79Jul 6, 2018Updated 7 years ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆28Feb 18, 2022Updated 4 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- exemplar code to download all option chains for a symbol using pyetrade (V1 Etrade API)☆10Sep 28, 2021Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Aug 28, 2023Updated 2 years ago
- Verilog implementation of MC68851 Memory Management Unit☆13Feb 26, 2018Updated 8 years ago
- A first bare bones paralleled implementation of Go Explore as described by the Uber Engineering blog post☆46Jan 25, 2019Updated 7 years ago