Alternatives and similar repositories for dnn-accelerator

Users that are interested in dnn-accelerator are comparing it to the libraries listed below

• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆29Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• tancheng / CGRA-Bench
  ☆15Updated 3 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 3 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆58Updated 3 years ago
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆68Updated 5 months ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆34Updated 6 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆26Updated last year
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆60Updated 10 months ago
• hngenc / stellar
  ☆31Updated 9 months ago
• sarchlab / zeonica
  Zeonica is a simulator for CGRA and Wafer-Scale Accelerators.
  ☆10Updated 4 months ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆83Updated last year
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 6 months ago
• maestro-project / gamma
  ☆41Updated last year
• StanfordAHA / aha
  ☆60Updated this week
• Xilinx / merlin-compiler
  ☆58Updated 2 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆81Updated 6 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• icgrp / hipr
  ☆16Updated 2 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆92Updated last year
• he-actlab / planaria.code
  ☆29Updated 3 years ago