jianyicheng / iiProverLinks
An LLVM pass to prove that an II works for the given loop for Vitis HLS
☆11Updated 3 years ago
Alternatives and similar repositories for iiProver
Users that are interested in iiProver are comparing it to the libraries listed below
Sorting:
- ☆27Updated 7 years ago
- DASS HLS Compiler☆29Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 6 months ago
- ☆15Updated 2 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- ☆24Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆59Updated 11 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- A hardware synthesis framework with multi-level paradigm☆40Updated 6 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- ILA Model Database☆23Updated 4 years ago
- ☆17Updated 3 weeks ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- DATuner Repository☆18Updated 6 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆18Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 3 weeks ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Papers, Posters, Presentations, Documentation...☆19Updated last year
- A Hardware Pipeline Description Language☆45Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 5 months ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- ☆36Updated 4 years ago