jianyicheng / iiProver
An LLVM pass to prove that an II works for the given loop for Vitis HLS
☆11Updated 3 years ago
Alternatives and similar repositories for iiProver:
Users that are interested in iiProver are comparing it to the libraries listed below
- DASS HLS Compiler☆29Updated last year
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated last month
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- ☆15Updated 2 years ago
- A tool to generate optimized hardware files for univariate functions.☆27Updated 11 months ago
- ☆26Updated 7 years ago
- ☆23Updated 4 years ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 6 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆16Updated 6 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆12Updated 2 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- Polyhedral High-Level Synthesis in MLIR☆30Updated last year
- ☆39Updated last month
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆27Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago