pku-liang / popaLinks
A unified programming framework for high and portable performance across FPGAs and GPUs
☆11Updated 9 months ago
Alternatives and similar repositories for popa
Users that are interested in popa are comparing it to the libraries listed below
Sorting:
- ☆13Updated 4 years ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆21Updated last year
- MAGIS: Memory Optimization via Coordinated Graph Transformation and Scheduling for DNN (ASPLOS'24)☆56Updated last year
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆14Updated last month
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- EQueue Dialect☆41Updated 3 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 3 years ago
- ☆18Updated 2 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Updated last year
- ☆31Updated 3 years ago
- Polyhedral High-Level Synthesis in MLIR☆35Updated 2 years ago
- agile hardware-software co-design☆52Updated 4 years ago
- ☆24Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆33Updated last year
- ☆38Updated 3 years ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆28Updated 3 years ago
- ☆17Updated 9 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆32Updated last year
- TileFlow is a performance analysis tool based on Timeloop for fusion dataflows☆66Updated last year
- Asynchronous semantics for architectural simulation and synthesis.☆64Updated last week
- Sparse kernels for GNNs based on TVM☆17Updated 5 years ago
- Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators☆120Updated 3 years ago
- A source-to-source compiler for optimizing CUDA dynamic parallelism by aggregating launches☆15Updated 6 years ago
- TiledLower is a Dataflow Analysis and Codegen Framework written in Rust.☆14Updated last year
- ☆28Updated 2 years ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Updated 3 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆18Updated last year
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- Heron: Automatically Constrained High-Performance Library Generation for Deep Learning Accelerators☆23Updated last year