pku-liang / popaLinks
A unified programming framework for high and portable performance across FPGAs and GPUs
☆11Updated 5 months ago
Alternatives and similar repositories for popa
Users that are interested in popa are comparing it to the libraries listed below
Sorting:
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆13Updated 3 months ago
- EQueue Dialect☆40Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- agile hardware-software co-design☆50Updated 3 years ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆21Updated 9 months ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 3 years ago
- ☆18Updated 2 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆24Updated 8 months ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated 11 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆28Updated last year
- ☆13Updated 3 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 7 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆16Updated 10 months ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- ☆24Updated 4 years ago
- ☆22Updated 6 months ago
- ☆38Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- ☆28Updated 2 years ago
- ☆17Updated 5 months ago
- Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization☆30Updated 9 months ago
- MAGIS: Memory Optimization via Coordinated Graph Transformation and Scheduling for DNN (ASPLOS'24)☆53Updated last year
- ☆14Updated 3 years ago
- Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators☆115Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated last year
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Updated 2 years ago