Alternatives and similar repositories for personal

Users that are interested in personal are comparing it to the libraries listed below

• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆81Updated 6 years ago
• StanfordAHA / aha
  ☆60Updated this week
• suchandler96 / gem5-NVDLA
  ☆34Updated 5 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆92Updated last year
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆60Updated 2 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago
• hngenc / stellar
  ☆31Updated 10 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆77Updated 6 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆30Updated 2 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆26Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 11 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆129Updated 5 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆136Updated 2 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆60Updated 10 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• zeasa / nvdla-compiler
  ☆46Updated 5 years ago
• lana555 / dynamatic
  ☆87Updated last year
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆40Updated 7 months ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆52Updated 8 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆50Updated 3 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆83Updated last year
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆157Updated 2 years ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago