AlexMontgomerie / fpgaconvnet-hlsLinks
☆32Updated 11 months ago
Alternatives and similar repositories for fpgaconvnet-hls
Users that are interested in fpgaconvnet-hls are comparing it to the libraries listed below
Sorting:
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆45Updated last year
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆30Updated 11 months ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆52Updated last year
- ☆59Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- NeuraLUT-Assemble☆41Updated last month
- ☆35Updated 6 years ago
- Verilog implementation of Softmax function☆71Updated 3 years ago
- ☆72Updated 2 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆93Updated 4 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆27Updated 3 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆91Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆97Updated 8 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- ☆37Updated 6 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆92Updated this week
- ☆22Updated 3 years ago
- ☆29Updated 6 months ago
- Train and deploy LUT-based neural networks on FPGAs☆98Updated last year
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆26Updated last month
- FPGA based Vision Transformer accelerator (Harvard CS205)☆131Updated 8 months ago
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Updated 3 years ago
- Open-source of MSD framework☆16Updated 2 years ago