A polyhedral compiler for hardware accelerators
☆59Jul 24, 2024Updated last year
Alternatives and similar repositories for clockwork
Users that are interested in clockwork are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆105Jun 27, 2022Updated 3 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆129Jun 11, 2024Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Mar 29, 2021Updated 5 years ago
- ☆82Feb 7, 2025Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆55Jul 17, 2023Updated 2 years ago
- ☆30Oct 16, 2022Updated 3 years ago
- HeteroCL-MLIR dialect for accelerator design☆42Sep 18, 2024Updated last year
- ☆17Updated this week
- ☆11Sep 14, 2020Updated 5 years ago
- ☆62Aug 4, 2023Updated 2 years ago
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained. Community-maintained version with binar…☆188Mar 8, 2026Updated last month
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆22Oct 31, 2024Updated last year
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆240Dec 8, 2022Updated 3 years ago
- Time-sensitive affine types for predictable hardware generation☆150Jan 5, 2026Updated 3 months ago
- ☆24Nov 10, 2020Updated 5 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆338Apr 20, 2024Updated 2 years ago
- ☆62Updated this week
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- ☆37Jun 1, 2022Updated 3 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Oct 8, 2018Updated 7 years ago
- PolyMage is a domain-specific language and optimizing code generator for auto-parallelisation☆14Jul 15, 2016Updated 9 years ago
- Intermediate Language (IL) for Hardware Accelerator Generators☆592Apr 20, 2026Updated last week
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆98Jan 29, 2026Updated 2 months ago
- Next generation CGRA generator☆120Updated this week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆25May 9, 2019Updated 6 years ago
- ☆40Sep 17, 2021Updated 4 years ago
- Bridging polyhedral analysis tools to the MLIR framework☆119Sep 9, 2023Updated 2 years ago
- Pono: A flexible and extensible SMT-based model checker☆122Updated this week
- Skeletonide is a parallel implementation of Zhang-Suen morphological thinning algorithm written in Halide-lang. Use it for fast skeletoni…☆14Oct 21, 2020Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆48Apr 4, 2022Updated 4 years ago
- A domain-specific language and compiler for image processing☆78Mar 20, 2021Updated 5 years ago