Alternatives and similar repositories for clockwork

Users that are interested in clockwork are comparing it to the libraries listed below

• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆82Updated 7 months ago
• Xilinx / merlin-compiler
  ☆58Updated 2 years ago
• lana555 / dynamatic
  ☆87Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆81Updated 6 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆40Updated 8 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆114Updated this week
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated 2 months ago
• StanfordAHA / aha
  ☆60Updated this week
• icgrp / hipr
  ☆16Updated 2 years ago
• sfu-arch / muir
  ☆24Updated 4 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆61Updated 11 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆113Updated last year
• stephenneuendorffer / vyasa
  Xilinx Modifications to Halide
  ☆13Updated 4 years ago
• wincle626 / HLS_Legup
  ☆28Updated 7 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆74Updated 3 weeks ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆60Updated 2 months ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• StanfordAHA / doc
  Papers, Posters, Presentations, Documentation...
  ☆19Updated last year
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆69Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated 2 weeks ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated 11 months ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 2 years ago