UCLA-VAST / AutoDSELinks
ACM TODAES Best Paper Award, 2022
☆26Updated last year
Alternatives and similar repositories for AutoDSE
Users that are interested in AutoDSE are comparing it to the libraries listed below
Sorting:
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- ☆72Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- ☆41Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated last year
- An HBM FPGA based SpMV Accelerator☆13Updated 11 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- ☆71Updated 5 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆56Updated 4 months ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- agile hardware-software co-design☆50Updated 3 years ago
- ☆57Updated 5 months ago
- ☆16Updated 2 years ago
- Heterogenous ML accelerator☆19Updated 3 months ago
- ☆13Updated 2 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- ☆25Updated last year
- ☆10Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆30Updated 9 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month