Alternatives and similar repositories for pylog:

Users that are interested in pylog are comparing it to the libraries listed below

• Xilinx / merlin-compiler
  ☆57Updated last year
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆89Updated 5 months ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆52Updated last year
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆55Updated 3 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆48Updated last month
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 5 months ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆24Updated last year
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 7 months ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated last year
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 3 years ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆19Updated 7 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆45Updated this week
• UIUC-ChenLab / Nimblock
  ☆11Updated last year
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆28Updated this week
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆79Updated last year
• StanfordAHA / aha
  ☆55Updated this week
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 2 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆69Updated 5 years ago
• pnnl / soda-opt
  ☆42Updated last week
• pku-liang / HASCO
  agile hardware-software co-design
  ☆47Updated 3 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆48Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• sfu-arch / SpGEMM
  ☆35Updated 3 years ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year