hst10 / pylogLinks
PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow
☆69Updated 2 years ago
Alternatives and similar repositories for pylog
Users that are interested in pylog are comparing it to the libraries listed below
Sorting:
- ☆61Updated 8 months ago
- EQueue Dialect☆41Updated 3 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆60Updated 2 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- ☆61Updated last week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆106Updated last year
- CGRA Compilation Framework☆88Updated 2 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆20Updated 8 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆96Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆80Updated 6 years ago
- ☆30Updated 6 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆175Updated 3 months ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 10 months ago
- agile hardware-software co-design☆52Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆54Updated 3 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- HeteroCL-MLIR dialect for accelerator design☆42Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- ☆72Updated 2 years ago