hst10 / pylogLinks
PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow
☆66Updated 2 years ago
Alternatives and similar repositories for pylog
Users that are interested in pylog are comparing it to the libraries listed below
Sorting:
- EQueue Dialect☆40Updated 3 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- A high-level performance analysis tool for FPGA-based accelerators☆20Updated 8 years ago
- ☆29Updated 6 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago
- ☆58Updated last year
- ☆53Updated 2 months ago
- ☆59Updated last week
- ACM TODAES Best Paper Award, 2022☆25Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- A hardware synthesis framework with multi-level paradigm☆39Updated 4 months ago
- ☆35Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- DASS HLS Compiler☆29Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆13Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆46Updated 2 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆36Updated this week
- ☆24Updated 4 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 2 weeks ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year