hst10 / pylogLinks
PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow
☆69Updated 2 years ago
Alternatives and similar repositories for pylog
Users that are interested in pylog are comparing it to the libraries listed below
Sorting:
- ☆62Updated 10 months ago
- EQueue Dialect☆41Updated 3 years ago
- ☆30Updated 6 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- ☆60Updated 2 years ago
- ☆72Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆177Updated 5 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆61Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆62Updated this week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆24Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Updated last month
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- ☆42Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆43Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- ☆17Updated 2 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago