sharc-lab / RealProbeLinks
☆12Updated 6 months ago
Alternatives and similar repositories for RealProbe
Users that are interested in RealProbe are comparing it to the libraries listed below
Sorting:
- A fast, accurate trace-based simulator for High-Level Synthesis.☆69Updated 6 months ago
- ☆13Updated 2 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆43Updated 3 weeks ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A research shell for Alveo V80☆17Updated last month
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆25Updated 5 months ago
- ☆59Updated 2 years ago
- Processing in Memory Emulation☆22Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆65Updated 3 weeks ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆18Updated last week
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆67Updated 2 weeks ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- ☆14Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- ☆66Updated last week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- ☆59Updated 6 months ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆78Updated 6 years ago
- ☆72Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 2 months ago