Alternatives and similar repositories for confuciux

Users that are interested in confuciux are comparing it to the libraries listed below

• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 3 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆83Updated 2 years ago
• maestro-project / gamma
  ☆41Updated last year
• he-actlab / planaria.code
  ☆29Updated 3 years ago
• ucb-bar / MoCA
  ☆28Updated 2 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆57Updated 5 months ago
• hsharma35 / bitfusion
  Simulator for BitFusion
  ☆101Updated 5 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• maestro-project / magma
  ☆16Updated 3 years ago
• isakedo / DNNsim
  ☆35Updated 5 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• ucb-bar / dosa
  DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
  ☆17Updated 11 months ago
• pku-liang / TENET
  An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…
  ☆86Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 3 years ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆19Updated 4 months ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆38Updated 2 years ago
• Accelergy-Project / pytorch2timeloop-converter
  ☆11Updated 11 months ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 11 months ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆50Updated 3 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆84Updated last year
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆110Updated 5 years ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆90Updated 4 months ago
• Aayush-Ankit / puma-simulator
  [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…
  ☆66Updated 2 years ago
• BradMcDanel / column-combine
  ☆27Updated 5 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• zjjzby / GNN-hardware-acceleration-paper
  This repo is to collect the state-of-the-art GNN hardware acceleration paper
  ☆54Updated 4 years ago