maestro-project / confuciuxLinks
☆33Updated 3 years ago
Alternatives and similar repositories for confuciux
Users that are interested in confuciux are comparing it to the libraries listed below
Sorting:
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆41Updated 11 months ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- ☆16Updated 2 years ago
- ☆25Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆64Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆36Updated last year
- ☆10Updated 2 years ago
- Heterogenous ML accelerator☆18Updated 3 weeks ago
- ☆34Updated 4 years ago
- ☆28Updated 2 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- ☆31Updated 3 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆67Updated 2 months ago
- ☆26Updated last year
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆15Updated 7 months ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- Simulator for BitFusion☆99Updated 4 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last month
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated 10 months ago
- ☆27Updated 2 months ago
- A general framework for optimizing DNN dataflow on systolic array☆36Updated 4 years ago
- HW accelerator mapping optimization framework for in-memory computing☆24Updated this week
- ☆11Updated 7 months ago