maestro-project / confuciux
☆33Updated 3 years ago
Alternatives and similar repositories for confuciux:
Users that are interested in confuciux are comparing it to the libraries listed below
- ☆39Updated 10 months ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆16Updated 2 years ago
- ☆25Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Simulator for BitFusion☆99Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆13Updated 6 months ago
- ☆26Updated last year
- Tool for optimize CNN blocking☆94Updated 5 years ago
- ☆34Updated 4 years ago
- EQueue Dialect☆40Updated 3 years ago
- ☆10Updated 6 months ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆18Updated 9 months ago
- agile hardware-software co-design☆46Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆64Updated 2 years ago
- ☆10Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last week
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆14Updated 3 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆30Updated 11 months ago
- HW accelerator mapping optimization framework for in-memory computing☆22Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- Open-source artifacts and codes of our MICRO'23 paper titled “Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi…☆37Updated last year
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆71Updated 2 years ago
- ☆70Updated 5 years ago
- A co-design architecture on sparse attention☆52Updated 3 years ago