hanchenye / polyaieLinks
An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE
☆16Updated 3 years ago
Alternatives and similar repositories for polyaie
Users that are interested in polyaie are comparing it to the libraries listed below
Sorting:
- Xilinx Modifications to Halide☆13Updated 4 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆24Updated 10 months ago
- Polyhedral High-Level Synthesis in MLIR☆34Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- EQueue Dialect☆39Updated 3 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated last year
- ☆36Updated 4 years ago
- agile hardware-software co-design☆52Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- ☆21Updated last week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆61Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆61Updated 3 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆30Updated 9 months ago
- ☆36Updated 6 months ago
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆31Updated 11 months ago
- ☆24Updated 4 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- ☆58Updated 2 years ago
- CGRA framework with vectorization support.☆35Updated last week
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆13Updated 5 months ago
- A graph linear algebra overlay☆51Updated 2 years ago