Reconfigurable-Computing / HLStoFPGA
☆12Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for HLStoFPGA
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆12Updated 8 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated last year
- ☆21Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- A tool for those who want to use Vivado's batch mode more easily☆15Updated 4 years ago
- FPU Generator☆20Updated 3 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆14Updated last month
- DASS HLS Compiler☆27Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- ☆31Updated last month
- ☆13Updated last year
- Wraps the NVDLA project for Chipyard integration☆19Updated 8 months ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Verilog behavioral description of various memories☆30Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- corundum work on vu13p☆17Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆19Updated 3 months ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆21Updated last month
- Chisel Cheatsheet☆31Updated last year
- ☆36Updated last week
- ☆22Updated 5 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆37Updated 2 years ago