Reconfigurable-Computing / HLStoFPGALinks
☆12Updated 2 years ago
Alternatives and similar repositories for HLStoFPGA
Users that are interested in HLStoFPGA are comparing it to the libraries listed below
Sorting:
- ☆29Updated last month
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated last month
- Reconfigurable Binary Engine☆16Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- HLS for Networks-on-Chip☆34Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- corundum work on vu13p☆18Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated 3 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 2 weeks ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆15Updated 2 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 9 months ago
- ☆62Updated this week
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- ☆33Updated 2 months ago
- Network on Chip for MPSoC☆26Updated last week
- FPU Generator☆20Updated 3 years ago