Reconfigurable-Computing / HLStoFPGALinks
☆12Updated 3 years ago
Alternatives and similar repositories for HLStoFPGA
Users that are interested in HLStoFPGA are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Benchmarks for High-Level Synthesis☆10Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- ☆11Updated 3 years ago
- corundum work on vu13p☆23Updated 2 years ago
- The official NaplesPU hardware code repository☆22Updated 6 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- ☆29Updated 8 years ago
- FPU Generator☆20Updated 4 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 8 months ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated 3 weeks ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Updated last year
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆26Updated 7 years ago
- ☆29Updated last year
- ☆90Updated this week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- ☆20Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Updated 3 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ☆31Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆44Updated 11 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- Chisel Cheatsheet☆35Updated 2 years ago
- ☆33Updated 2 months ago
- Wraps the NVDLA project for Chipyard integration☆22Updated 5 months ago