Reconfigurable-Computing / HLStoFPGALinks
☆12Updated 3 years ago
Alternatives and similar repositories for HLStoFPGA
Users that are interested in HLStoFPGA are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Updated 2 years ago
- Benchmarks for High-Level Synthesis☆10Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- corundum work on vu13p☆22Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Wraps the NVDLA project for Chipyard integration☆22Updated 3 months ago
- ☆29Updated 8 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 7 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- ☆36Updated 4 years ago
- DDR4 Simulation Project in System Verilog☆43Updated 11 years ago
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Updated last year
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- ☆28Updated 6 years ago
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 4 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- ☆17Updated 2 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated this week
- CNN accelerator☆27Updated 8 years ago
- ☆29Updated last year
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago