A collection of URLs related to High Level Synthesis (HLS).
☆13Jun 26, 2021Updated 4 years ago
Alternatives and similar repositories for high-level-synthesis-resources
Users that are interested in high-level-synthesis-resources are comparing it to the libraries listed below
Sorting:
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 5 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- [CVPR 2022] DiSparse: Disentangled Sparsification for Multitask Model Compression☆14Sep 6, 2022Updated 3 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- Convert C files into Verilog☆21Jan 27, 2019Updated 7 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 8 years ago
- ☆17Nov 20, 2022Updated 3 years ago
- ☆16Jan 20, 2021Updated 5 years ago
- The second place winner for DAC-SDC 2020☆99Apr 23, 2022Updated 3 years ago
- ☆19Mar 17, 2021Updated 4 years ago
- ☆19Mar 16, 2022Updated 3 years ago
- TQT's pytorch implementation.☆21Dec 17, 2021Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Jun 18, 2020Updated 5 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆91Nov 25, 2018Updated 7 years ago
- ☆19Aug 9, 2022Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28May 11, 2022Updated 3 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆33Aug 1, 2020Updated 5 years ago
- ☆32Mar 31, 2025Updated 11 months ago
- ☆30Apr 26, 2019Updated 6 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- ACM TODAES Best Paper Award, 2022☆32Oct 24, 2023Updated 2 years ago
- DASS HLS Compiler☆29Oct 4, 2023Updated 2 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆114Feb 22, 2021Updated 5 years ago
- ☆72Feb 16, 2023Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Jul 8, 2020Updated 5 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 3 months ago
- Post-training sparsity-aware quantization☆34Feb 26, 2023Updated 3 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Nov 14, 2021Updated 4 years ago
- A Python implementation of the Hopfield network used to solve the traveling salesman problem☆10Apr 11, 2019Updated 6 years ago
- Convolutional Channel-wise Competitive Learning for the Forward-Forward Algorithm. AAAI 2024☆12Jun 27, 2024Updated last year
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- HPA2021 solution (3rd place)☆10Oct 13, 2021Updated 4 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- ☆35Mar 1, 2019Updated 7 years ago