Alternatives and similar repositories for high-level-synthesis-resources:

Users that are interested in high-level-synthesis-resources are comparing it to the libraries listed below

• Kareem-Emad / DCNN-Accelerator
  Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
  ☆12Updated 5 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆25Updated 4 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• Blaok / soda
  Stencil with Optimized Dataflow Architecture
  ☆12Updated last year
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆34Updated last week
• ChrisZonghaoLi / cnn_conv_accelerator
  A Fix-pointed Rudimentary CNN Convolution Accelerator
  ☆14Updated 4 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆30Updated last year
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆3Updated 3 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆39Updated 6 months ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• racosa / cnn-accelerator
  A Convolutional Neural Network (CNN) hardware accelerator for image recognition
  ☆13Updated 5 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆24Updated 4 years ago
• Hosseinabady / SDSoC-Benchmarks
  ☆16Updated 4 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• dac-sdc / fpga_starter_2023
  ☆8Updated last year
• mnnuahg / StamicCGRA
  A static dataflow CGRA with dynamic dataflow execution capability
  ☆10Updated 3 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• TUD-ADS / HiFlipVX
  ☆16Updated 2 years ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆16Updated 4 years ago
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated last year
• kkiningh / cs231n-project
  CNN accelerator
  ☆28Updated 7 years ago
• nqHITSZ / Systolic-Array
  course design
  ☆22Updated 7 years ago
• template-hls / template-hls-float
  ☆29Updated 5 years ago