ninfueng / high-level-synthesis-resources
A collection of URLs related to High Level Synthesis (HLS).
☆12Updated 3 years ago
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- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆27Updated 5 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- ☆12Updated 2 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- CNN accelerator☆27Updated 7 years ago
- ☆16Updated 2 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 4 years ago
- ☆4Updated 4 years ago
- ☆59Updated 2 weeks ago
- Stencil with Optimized Dataflow Architecture☆12Updated last year
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 11 months ago
- course design☆22Updated 7 years ago
- ☆16Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆23Updated 3 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 2 months ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆13Updated 5 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago