ninfueng / high-level-synthesis-resourcesLinks
A collection of URLs related to High Level Synthesis (HLS).
☆13Updated 4 years ago
Alternatives and similar repositories for high-level-synthesis-resources
Users that are interested in high-level-synthesis-resources are comparing it to the libraries listed below
Sorting:
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆27Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Stencil with Optimized Dataflow Architecture☆12Updated last year
- ☆15Updated 4 months ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13Updated 6 years ago
- Algorithmic C Machine Learning Library☆26Updated 10 months ago
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- ☆17Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆16Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Updated 5 years ago
- ☆72Updated 2 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 2 months ago
- Engineering Program on RTL Design for FPGA Accelerator☆31Updated 5 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- CNN accelerator☆27Updated 8 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- ☆36Updated 4 years ago