The-OpenROAD-Project / asap7
☆76Updated 2 months ago
Related projects: ⓘ
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆137Updated 4 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆23Updated 3 years ago
- ☆108Updated 3 years ago
- This is a tutorial on standard digital design flow☆71Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆57Updated 3 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆30Updated 2 months ago
- ☆38Updated this week
- Introductory course into static timing analysis (STA).☆54Updated 5 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆58Updated 2 years ago
- ☆35Updated last week
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆26Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆72Updated this week
- A complete open-source design-for-testing (DFT) Solution☆131Updated 3 weeks ago
- ☆34Updated 5 months ago
- A Fast, Low-Overhead On-chip Network☆115Updated this week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆60Updated 3 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆22Updated 4 years ago
- ☆49Updated 10 months ago
- Material for OpenROAD Tutorial at DAC 2020☆45Updated last year
- AMC: Asynchronous Memory Compiler☆44Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆130Updated 3 months ago
- Logic synthesis and ABC based optimization☆44Updated this week
- IEEE 754 floating point library in system-verilog and vhdl☆53Updated 3 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆30Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆72Updated 5 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆41Updated 3 years ago
- ☆35Updated 2 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆75Updated 9 months ago