The-OpenROAD-Project / asap7Links
☆208Updated 8 months ago
Alternatives and similar repositories for asap7
Users that are interested in asap7 are comparing it to the libraries listed below
Sorting:
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆191Updated 5 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆274Updated last week
- ☆183Updated 4 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆51Updated last year
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆232Updated 2 weeks ago
- Introductory course into static timing analysis (STA).☆99Updated 4 months ago
- Logic synthesis and ABC based optimization☆50Updated 2 weeks ago
- ☆44Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆181Updated 11 months ago
- A complete open-source design-for-testing (DFT) Solution☆168Updated 2 months ago
- ☆93Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆301Updated last month
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆80Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆133Updated 7 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆193Updated this week
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆80Updated 3 years ago
- Collection of digital hardware modules & projects (benchmarks)☆69Updated last week
- Network on Chip Implementation written in SytemVerilog☆193Updated 3 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated this week
- An AXI4 crossbar implementation in SystemVerilog☆180Updated 2 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆91Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆221Updated last week
- AIB Generator: Analog hardware compiler for AIB PHY☆35Updated 5 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆97Updated 4 months ago
- ☆89Updated 4 months ago