Centre-for-Hardware-Security / asap7_reference_designLinks
reference block design for the ASAP7nm library in Cadence Innovus
☆47Updated last year
Alternatives and similar repositories for asap7_reference_design
Users that are interested in asap7_reference_design are comparing it to the libraries listed below
Sorting:
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆181Updated 5 years ago
- ☆178Updated 4 months ago
- ☆43Updated 10 months ago
- Introductory course into static timing analysis (STA).☆96Updated last month
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated last week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆127Updated 7 years ago
- ☆157Updated 3 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 3 months ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- A Standalone Structural Verilog Parser☆96Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆19Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆35Updated 5 years ago
- ☆78Updated last week
- ☆45Updated last year
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆171Updated 8 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- IDEA project source files☆107Updated 8 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 2 months ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆93Updated last month
- An AXI4 crossbar implementation in SystemVerilog☆164Updated last month
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆20Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆69Updated last year
- ☆34Updated 6 years ago