☆20Apr 8, 2026Updated 3 weeks ago
Alternatives and similar repositories for instruction-decoder
Users that are interested in instruction-decoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆19Nov 23, 2023Updated 2 years ago
- Iron: selectively turn RISC-V binaries into hardware☆23Jun 8, 2023Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆52Apr 19, 2026Updated last week
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- WAL enables programmable waveform analysis.☆177Nov 10, 2025Updated 5 months ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 4 years ago
- Handle Fast Signal Traces (fst) in Python☆14Jun 11, 2025Updated 10 months ago
- FreeRTOS port for the RISC-V Virtual Prototype☆14Nov 9, 2020Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆19Apr 27, 2024Updated 2 years ago
- Demonstrating systemverilog, verilator and google test for verification☆10Mar 3, 2021Updated 5 years ago
- ZPU - the worlds smallest 32 bit CPU with GCC toolchain☆16Jul 17, 2014Updated 11 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- A command-line tool for displaying vcd waveforms.☆69Feb 19, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A library for programming iCE40 FPGA from Lattice Semi☆13Mar 22, 2024Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆34Apr 13, 2025Updated last year
- Block diagrams in ASCII☆18Oct 17, 2025Updated 6 months ago
- ☆19Apr 9, 2026Updated 3 weeks ago
- RISCV Core written in Calyx☆17Aug 16, 2024Updated last year
- ☆27Jan 8, 2023Updated 3 years ago
- A library of components for RISC-V implementations in Haskell CLaSH☆13Mar 24, 2017Updated 9 years ago
- Example of an ELF parser to learn about the ELF format☆11Oct 6, 2024Updated last year
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆29Nov 10, 2025Updated 5 months ago
- ☆10Nov 8, 2019Updated 6 years ago
- ☆41Jan 23, 2024Updated 2 years ago
- ☆16Oct 5, 2021Updated 4 years ago
- A complete Risc-v RV32I emulator in Rust☆28Jan 28, 2024Updated 2 years ago
- A strange and sweet language made for gamejams☆11Feb 17, 2024Updated 2 years ago
- Use multiple bibliographies in a single Typst document—Moved to https://codeberg.org/ensko/typst-alexandria☆26Dec 11, 2025Updated 4 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆50Dec 30, 2024Updated last year
- Playground for VGA projects on Tiny Tapeout☆73Apr 18, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- VSCodium for LoongArch with system-wide Electron.☆12Dec 14, 2023Updated 2 years ago
- UART 16550 core☆39Jul 17, 2014Updated 11 years ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆31Nov 28, 2025Updated 5 months ago
- Unified Coverage Interoperability Standard (UCIS)☆14Jan 28, 2026Updated 3 months ago
- A Python to VHDL compiler☆17Apr 28, 2025Updated last year
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 3 years ago
- GNU Make Standard Library: a library of functions written for GNU Make using GNU Make's built in functions (full CVS history from https:/…☆12Nov 29, 2017Updated 8 years ago