ics-jku / instruction-decoderLinks
☆14Updated last month
Alternatives and similar repositories for instruction-decoder
Users that are interested in instruction-decoder are comparing it to the libraries listed below
Sorting:
- Platform Level Interrupt Controller☆41Updated last year
- CMake based hardware build system☆29Updated 2 weeks ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- RISC-V Nox core☆65Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- An automatic clock gating utility☆50Updated 3 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- An implementation of RISC-V☆35Updated last week
- A configurable SRAM generator☆53Updated last week
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Mirror of tachyon-da cvc Verilog simulator☆47Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆46Updated 9 months ago
- Characterizer☆28Updated last month
- ☆96Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- a Python framework for managing embedded HW/SW projects☆17Updated this week
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 2 months ago
- ☆33Updated 2 years ago
- ☆47Updated 3 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆13Updated 3 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- Library of open source Process Design Kits (PDKs)☆48Updated 3 weeks ago