bespoke-silicon-group / bsg_fakeramLinks
fakeram generator for use by researchers who do not have access to commercial ram generators
☆37Updated 2 years ago
Alternatives and similar repositories for bsg_fakeram
Users that are interested in bsg_fakeram are comparing it to the libraries listed below
Sorting:
- A configurable SRAM generator☆53Updated this week
- sram/rram/mram.. compiler☆38Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆66Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- Open source process design kit for 28nm open process☆60Updated last year
- ☆44Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 9 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- SRAM☆22Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Project repo for the POSH on-chip network generator☆49Updated 5 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated this week
- Next generation CGRA generator☆113Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- ☆32Updated 7 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆33Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated 3 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆49Updated 4 months ago
- Library of open source Process Design Kits (PDKs)☆50Updated last week
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago