bespoke-silicon-group / bsg_fakeramLinks
fakeram generator for use by researchers who do not have access to commercial ram generators
☆37Updated 2 years ago
Alternatives and similar repositories for bsg_fakeram
Users that are interested in bsg_fakeram are comparing it to the libraries listed below
Sorting:
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- Open source process design kit for 28nm open process☆59Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- A configurable SRAM generator☆53Updated this week
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 7 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- ☆44Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- ☆66Updated 2 years ago
- Project repo for the POSH on-chip network generator☆48Updated 3 months ago
- ☆76Updated this week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A Standalone Structural Verilog Parser☆93Updated 3 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago
- ☆32Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- ☆26Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 9 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- SRAM☆22Updated 4 years ago
- ideas and eda software for vlsi design☆50Updated 3 weeks ago
- Introductory course into static timing analysis (STA).☆94Updated last week
- Open Source PHY v2☆29Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- YosysHQ SVA AXI Properties☆41Updated 2 years ago