bespoke-silicon-group / bsg_fakeramLinks
fakeram generator for use by researchers who do not have access to commercial ram generators
☆38Updated 2 years ago
Alternatives and similar repositories for bsg_fakeram
Users that are interested in bsg_fakeram are comparing it to the libraries listed below
Sorting:
- sram/rram/mram.. compiler☆42Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Open source process design kit for 28nm open process☆67Updated last year
- A configurable SRAM generator☆57Updated 2 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆91Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- ☆44Updated 5 years ago
- ☆67Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆31Updated 2 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated last week
- ☆58Updated 7 months ago
- SRAM☆22Updated 5 years ago
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆92Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 11 months ago
- Introductory course into static timing analysis (STA).☆99Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- ☆43Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 5 months ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- ☆106Updated 5 years ago
- ☆33Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆80Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- An automatic clock gating utility☆51Updated 6 months ago
- Open Source PHY v2☆31Updated last year