bespoke-silicon-group / bsg_fakeram

Related projects: ⓘ

• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆23Updated 3 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆44Updated 4 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆21Updated last year
• mortbopet / NetCracker
  NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…
  ☆14Updated 3 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆71Updated 3 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆72Updated 5 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆38Updated 4 years ago
• pulp-platform / svase
  ☆28Updated last week
• cornell-brg / alloy-asic
  ☆15Updated this week
• aolofsson / POSH
  ☆37Updated 4 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆45Updated 2 months ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆41Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆41Updated last week
• The-OpenROAD-Project / asap7
  ☆76Updated 2 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆38Updated last year
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆11Updated 8 years ago
• bsg-idea / uw_openroad_free45
  UW reference flow for Free45PDK and The OpenROAD Project
  ☆9Updated 4 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆19Updated 4 years ago
• marlls1989 / ascend-freepdk45
  A free standard cell library for SDDS-NCL circuits
  ☆22Updated last year
• eclufsc / libertyParser
  Mirror of Synopsys's Liberty parser library
  ☆17Updated 6 years ago
• IntelLabs / FloorSet
  ☆46Updated last month
• chipsalliance / aib-protocols
  ☆22Updated 7 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆48Updated last month
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆87Updated 5 months ago
• hyoukjun / OpenSMART
  Public release
  ☆45Updated 5 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆45Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆45Updated 4 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆54Updated 5 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆23Updated 4 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆57Updated 3 years ago