bespoke-silicon-group / bsg_fakeramLinks
fakeram generator for use by researchers who do not have access to commercial ram generators
☆37Updated 2 years ago
Alternatives and similar repositories for bsg_fakeram
Users that are interested in bsg_fakeram are comparing it to the libraries listed below
Sorting:
- A configurable SRAM generator☆54Updated last month
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 10 months ago
- Open source process design kit for 28nm open process☆61Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Project repo for the POSH on-chip network generator☆50Updated 6 months ago
- ☆44Updated 5 years ago
- ☆67Updated 2 years ago
- A Standalone Structural Verilog Parser☆97Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- SRAM☆22Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆47Updated 4 years ago
- ☆32Updated 8 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 4 months ago
- ☆31Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated last month
- ☆33Updated 5 years ago
- Python library for operations with VCD and other digital wave files☆52Updated 3 months ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated 11 months ago