bespoke-silicon-group / bsg_fakeramLinks
fakeram generator for use by researchers who do not have access to commercial ram generators
☆37Updated 2 years ago
Alternatives and similar repositories for bsg_fakeram
Users that are interested in bsg_fakeram are comparing it to the libraries listed below
Sorting:
- Open source process design kit for 28nm open process☆59Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated 3 weeks ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- ☆44Updated 5 years ago
- A configurable SRAM generator☆51Updated last week
- SRAM☆22Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- reference block design for the ASAP7nm library in Cadence Innovus☆44Updated last year
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Project repo for the POSH on-chip network generator☆46Updated 3 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 7 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆84Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- sram/rram/mram.. compiler☆35Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆33Updated 5 years ago
- ☆33Updated 5 years ago
- Advanced Architecture Labs with CVA6☆62Updated last year
- ☆32Updated 5 months ago
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago