The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
☆419Updated this week
Alternatives and similar repositories for OpenROAD-flow-scripts
Users that are interested in OpenROAD-flow-scripts are comparing it to the libraries listed below
Sorting:
- OpenSTA engine☆460Updated 2 weeks ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆326Updated this week
- Fully Open Source FASOC generators built on top of open-source EDA tools☆277Updated last month
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆251Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆319Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆285Updated 2 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆325Updated 2 months ago
- ☆298Updated 2 months ago
- A High-performance Timing Analysis Tool for VLSI Systems☆616Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆573Updated this week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆173Updated 5 years ago
- Common SystemVerilog components☆618Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆209Updated 6 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆279Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆488Updated 3 months ago
- The UVM written in Python☆424Updated last month
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆534Updated this week
- Magic VLSI Layout Tool☆539Updated last month
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- ☆160Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆390Updated last month
- An open-source static random access memory (SRAM) compiler.☆899Updated last month
- SystemVerilog to Verilog conversion☆627Updated last month
- lowRISC Style Guides☆425Updated 8 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆533Updated last week
- https://caravel-user-project.readthedocs.io☆198Updated 2 months ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆523Updated last year
- 100 Days of RTL☆365Updated 9 months ago
- SystemRDL 2.0 language compiler front-end☆251Updated 2 months ago
- ☆143Updated 3 years ago