Alternatives and similar repositories for OpenROAD-flow-scripts

Users that are interested in OpenROAD-flow-scripts are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆460Updated 2 weeks ago
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆326Updated this week
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆277Updated last month
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆251Updated 2 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆319Updated this week
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆285Updated 2 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆325Updated 2 months ago
• ALIGN-analoglayout / ALIGN-public
  ☆298Updated 2 months ago
• OpenTimer / OpenTimer
  A High-performance Timing Analysis Tool for VLSI Systems
  ☆616Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆573Updated this week
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆173Updated 5 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆618Updated last week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆209Updated 6 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆279Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆488Updated 3 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆424Updated last month
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆534Updated this week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆539Updated last month
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• The-OpenROAD-Project / asap7
  ☆160Updated 2 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆390Updated last month
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆899Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆627Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆425Updated 8 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆533Updated last week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆198Updated 2 months ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆523Updated last year
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆365Updated 9 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated 2 months ago
• ncsu-eda / FreePDK3
  ☆143Updated 3 years ago