Alternatives and similar repositories for OpenROAD-flow-scripts

Users that are interested in OpenROAD-flow-scripts are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆490Updated this week
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆346Updated this week
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆257Updated last week
• OpenTimer / OpenTimer
  A High-performance Timing Analysis Tool for VLSI Systems
  ☆637Updated 3 weeks ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆306Updated 5 months ago
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆284Updated last month
• ALIGN-analoglayout / ALIGN-public
  ☆308Updated last month
• pyuvm / pyuvm
  The UVM written in Python
  ☆445Updated 3 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆642Updated last week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆928Updated last month
• iic-jku / IIC-OSIC-TOOLS
  IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…
  ☆618Updated this week
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆580Updated this week
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆181Updated 5 years ago
• The-OpenROAD-Project / asap7
  ☆178Updated 4 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆446Updated last month
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆216Updated 9 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆386Updated 11 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆343Updated 5 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆653Updated last month
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆285Updated 2 months ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆186Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆516Updated 5 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆336Updated this week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆557Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆595Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆572Updated this week
• ncsu-eda / FreePDK3
  ☆157Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆403Updated this week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆211Updated 5 months ago
• OSCC-Project / iEDA
  An open-source EDA infrastructure and tools from netlist to GDS
  ☆404Updated last week