Alternatives and similar repositories for OpenROAD-flow-scripts

Users that are interested in OpenROAD-flow-scripts are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆480Updated last week
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆335Updated last week
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆257Updated 4 months ago
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆282Updated last week
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆329Updated 4 months ago
• OpenTimer / OpenTimer
  A High-performance Timing Analysis Tool for VLSI Systems
  ☆631Updated 2 years ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆301Updated 4 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆282Updated last month
• ALIGN-analoglayout / ALIGN-public
  ☆303Updated 3 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆434Updated this week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆214Updated 8 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆911Updated 2 months ago
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆557Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆581Updated 2 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆639Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆328Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆504Updated 4 months ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆178Updated 5 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆629Updated this week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆202Updated 4 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆327Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆395Updated last week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆543Updated this week
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆184Updated last month
• rggen / rggen
  Code generation tool for control and status registers
  ☆397Updated 3 weeks ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆368Updated 10 months ago
• The-OpenROAD-Project / asap7
  ☆169Updated 3 months ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆254Updated 3 months ago
• OSCC-Project / iEDA
  ☆381Updated this week