The-OpenROAD-Project / OpenROAD-flow-scripts

Related projects ⓘ

Alternatives and complementary repositories for OpenROAD-flow-scripts

• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆291Updated 2 weeks ago
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆412Updated 2 weeks ago
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆241Updated 3 weeks ago
• ALIGN-analoglayout / ALIGN-public
  ☆267Updated 2 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆297Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆518Updated this week
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆209Updated this week
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆233Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆438Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆564Updated 3 weeks ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆151Updated 4 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆526Updated this week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆255Updated last week
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆368Updated last week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆184Updated last week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆194Updated 3 weeks ago
• efabless / caravel
  Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆295Updated 2 weeks ago
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆495Updated this week
• pyuvm / pyuvm
  The UVM written in Python
  ☆374Updated 4 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆448Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆202Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆281Updated 2 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆836Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆371Updated 2 months ago
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆410Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• iic-jku / IIC-OSIC-TOOLS
  IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…
  ☆334Updated this week
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆151Updated last year