The-OpenROAD-Project / OpenROAD-flow-scriptsLinks
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
☆508Updated this week
Alternatives and similar repositories for OpenROAD-flow-scripts
Users that are interested in OpenROAD-flow-scripts are comparing it to the libraries listed below
Sorting:
- OpenSTA engine☆510Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆367Updated last week
- Fully Open Source FASOC generators built on top of open-source EDA tools☆295Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆271Updated 2 weeks ago
- ☆318Updated 3 months ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆624Updated last week
- ☆201Updated 7 months ago
- A High-performance Timing Analysis Tool for VLSI Systems☆665Updated 3 months ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆681Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆299Updated 2 weeks ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆316Updated 8 months ago
- An open-source static random access memory (SRAM) compiler.☆957Updated last week
- Magic VLSI Layout Tool☆575Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆219Updated last year
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆191Updated 5 years ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆356Updated 8 months ago
- ☆178Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆192Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆613Updated this week
- Machine Generated Analog IC Layout☆256Updated last year
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- SystemVerilog to Verilog conversion☆670Updated 4 months ago
- The UVM written in Python☆468Updated last week
- An open-source EDA infrastructure and tools from netlist to GDS☆441Updated this week
- Common SystemVerilog components☆666Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆534Updated last week
- Physical Design Flow from RTL to GDS using Opensource tools.☆112Updated 4 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆345Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆387Updated last week
- ☆352Updated 2 years ago