google / gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
☆393Updated last year
Alternatives and similar repositories for gf180mcu-pdk:
Users that are interested in gf180mcu-pdk are comparing it to the libraries listed below
- Fully Open Source FASOC generators built on top of open-source EDA tools☆273Updated 3 weeks ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆322Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆324Updated 2 months ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆527Updated 3 weeks ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆282Updated 2 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆208Updated 6 months ago
- https://caravel-user-project.readthedocs.io☆198Updated 2 months ago
- ☆111Updated last year
- Magic VLSI Layout Tool☆536Updated 3 weeks ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆475Updated last week
- ☆321Updated 2 years ago
- An open-source static random access memory (SRAM) compiler.☆894Updated last month
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆378Updated this week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆150Updated 11 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- FOSS Flow For FPGA☆386Updated 4 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆177Updated last week
- Example designs showing different ways to use F4PGA toolchains.☆275Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆282Updated this week
- Common SystemVerilog components☆608Updated 2 weeks ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆416Updated this week
- CORE-V Family of RISC-V Cores☆264Updated 2 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆278Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆249Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆485Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆318Updated this week
- OpenSTA engine☆459Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆528Updated 3 weeks ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆315Updated 4 months ago
- VeeR EL2 Core☆274Updated last week