Alternatives and similar repositories for freepdk-45nm

Users that are interested in freepdk-45nm are comparing it to the libraries listed below

• The-OpenROAD-Project / asap7
  ☆178Updated 5 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆258Updated 3 weeks ago
• ncsu-eda / FreePDK3
  ☆164Updated 3 years ago
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆37Updated 5 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆49Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆96Updated last month
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆221Updated 3 weeks ago
• vaughnbetz / COFFE
  ☆44Updated 11 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆74Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆188Updated 2 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆74Updated 3 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated 2 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆155Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆169Updated this week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆173Updated 9 months ago
• parallaxsw / OpenSTA
  ☆82Updated this week
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆75Updated last year
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆49Updated 2 weeks ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆90Updated 6 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆286Updated 3 months ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆76Updated 7 years ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆187Updated 3 months ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 4 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆128Updated 5 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆105Updated 4 years ago