mflowgen / freepdk-45nmLinks
ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
☆200Updated 5 years ago
Alternatives and similar repositories for freepdk-45nm
Users that are interested in freepdk-45nm are comparing it to the libraries listed below
Sorting:
- ☆232Updated 10 months ago
- ☆189Updated 4 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆280Updated last month
- A Fast, Low-Overhead On-chip Network☆265Updated last week
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- Logic synthesis and ABC based optimization☆52Updated 3 weeks ago
- reference block design for the ASAP7nm library in Cadence Innovus☆57Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆186Updated last year
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- Network on Chip Implementation written in SytemVerilog☆197Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- A complete open-source design-for-testing (DFT) Solution☆178Updated 5 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆309Updated 3 months ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 2 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆98Updated 6 years ago
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- ☆46Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆82Updated 3 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆118Updated 5 years ago
- ☆109Updated 6 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆41Updated 5 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆106Updated 7 months ago
- A Chisel RTL generator for network-on-chip interconnects☆225Updated 2 months ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated 2 years ago
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆21Updated last year