Alternatives and similar repositories for BTAssign

Users that are interested in BTAssign are comparing it to the libraries listed below

• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆142Updated 4 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆66Updated 4 months ago
• bu-icsg / TAP-2.5D
  ☆34Updated 4 years ago
• cuhk-eda / cu-gr-2
  ☆47Updated last year
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆82Updated last year
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆29Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆106Updated last year
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆54Updated 4 months ago
• EricLu1218 / Physical_Design_Automation
  NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…
  ☆42Updated 2 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated 2 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 5 months ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆138Updated 2 years ago
• TILOS-AI-Institute / MacroPlacement
  Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source
  ☆284Updated last month
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆44Updated last year
• ycchen218 / EDA-IRdrop-Prediction
  This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
  ☆32Updated 2 years ago
• ABKGroup / TritonRoute-WXL
  ☆34Updated 5 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆53Updated last year
• ycchen218 / EDA-Congestion-Prediction
  This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.
  ☆21Updated last year
• uvahotspot / HotSpot
  HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.
  ☆134Updated 2 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆57Updated 9 months ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆75Updated 7 years ago
• NVlabs / INSTA
  ☆88Updated 4 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆132Updated last year
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆85Updated 6 months ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆183Updated 5 months ago
• ABKGroup / NanGate45-Synopsys-Enablement
  ☆23Updated last month
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆138Updated 2 years ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆159Updated 6 months ago
• CODA-Team / AnalogGym
  ☆61Updated last week
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆93Updated 3 months ago