AUCOHL / DFFRAMLinks
Standard Cell Library based Memory Compiler using FF/Latch cells
☆162Updated last month
Alternatives and similar repositories for DFFRAM
Users that are interested in DFFRAM are comparing it to the libraries listed below
Sorting:
- Fabric generator and CAD tools.☆214Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- A complete open-source design-for-testing (DFT) Solution☆174Updated 4 months ago
- SystemVerilog synthesis tool☆223Updated 9 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- SystemVerilog frontend for Yosys☆186Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated this week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆196Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆308Updated 2 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆146Updated 2 years ago
- ☆183Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆178Updated last week
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- ☆86Updated 3 years ago
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- ☆223Updated 9 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated 3 weeks ago
- FuseSoC standard core library☆151Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆257Updated 3 weeks ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- SpinalHDL Hardware Math Library☆93Updated last year
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- RISC-V Verification Interface☆134Updated 3 weeks ago
- ☆122Updated 2 years ago