CODA-Team / AnalogGym
☆19Updated last month
Related projects ⓘ
Alternatives and complementary repositories for AnalogGym
- awesome-Analog-IC-Design-Automation☆29Updated last year
- ☆29Updated last year
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆10Updated 2 years ago
- ☆13Updated 4 months ago
- Analog Placement Quality Prediction☆19Updated last year
- ☆15Updated 3 years ago
- ☆28Updated 2 years ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated last year
- ☆19Updated this week
- ☆36Updated 7 months ago
- Artificial Netlist Generator☆32Updated 7 months ago
- Circuit release of the MAGICAL project☆29Updated 4 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆19Updated 2 months ago
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆26Updated 4 years ago
- ☆25Updated last year
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆63Updated 2 months ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆24Updated last year
- ☆20Updated 6 months ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆58Updated 2 weeks ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆30Updated this week
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of paper…☆39Updated last year
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆33Updated last month
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆11Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆35Updated last month
- ☆17Updated last year
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- GPU-based logic synthesis tool☆67Updated 3 months ago
- ☆23Updated 3 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆17Updated 4 months ago
- ☆50Updated 2 weeks ago