ckchengucsd / SMTCellUCSDLinks
Cell Layout Generation for DTCO/STCO Exploration Toolkit
☆21Updated 6 months ago
Alternatives and similar repositories for SMTCellUCSD
Users that are interested in SMTCellUCSD are comparing it to the libraries listed below
Sorting:
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 8 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆40Updated last year
- ☆18Updated 4 years ago
- Research paper based on or related to ABC.☆62Updated 3 weeks ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆55Updated 11 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- ☆29Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆34Updated 8 months ago
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- Arithmetic multiplier benchmarks☆11Updated 8 years ago
- ☆12Updated 2 years ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated last year
- ☆26Updated this week
- Collection of digital hardware modules & projects (benchmarks)☆74Updated this week
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Updated last year
- GPU-based logic synthesis tool☆97Updated last week
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Updated 3 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆25Updated 3 years ago
- ☆20Updated 3 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆33Updated last year
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆28Updated 7 months ago
- GNN-RE datasets for circuit recognition☆54Updated 2 years ago
- A Formal Verification Framework for Chisel☆18Updated last year
- ☆16Updated 2 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Updated 9 years ago
- ☆13Updated 2 years ago