Alternatives and similar repositories for OpenROAD

Users that are interested in OpenROAD are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenLane
  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…
  ☆1,637Updated 2 months ago
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆521Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆966Updated last month
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆527Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,173Updated last week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,108Updated this week
• OpenTimer / OpenTimer
  A High-performance Timing Analysis Tool for VLSI Systems
  ☆676Updated 4 months ago
• limbo018 / DREAMPlace
  Deep learning toolkit-enabled VLSI placement
  ☆895Updated 2 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,686Updated last week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆588Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,161Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,044Updated last week
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,151Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,022Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,250Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,414Updated last week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,695Updated 3 months ago
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,183Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,144Updated 6 months ago
• OSCC-Project / iEDA
  An open-source EDA infrastructure and tools from netlist to GDS
  ☆455Updated 3 weeks ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,554Updated last week
• berkeley-abc / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆1,079Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆757Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,363Updated 2 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,695Updated last month
• google / gf180mcu-pdk
  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
  ☆441Updated 2 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆747Updated 3 weeks ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆866Updated this week
• google / skywater-pdk
  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
  ☆3,330Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆677Updated last week