Alternatives and similar repositories for DTMF-Receiver-Logic-Synthesis-and-Physical-Design-

Users that are interested in DTMF-Receiver-Logic-Synthesis-and-Physical-Design- are comparing it to the libraries listed below

• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆24Updated last year
• shubhi704 / APB-Protocol
  ☆52Updated 4 years ago
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆38Updated 3 months ago
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆20Updated 6 months ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆69Updated last year
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆81Updated 4 years ago
• Devipriya1921 / VSDBabySoC_ICC2
  ☆14Updated 3 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆56Updated 8 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆89Updated 8 years ago
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆62Updated 2 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 5 months ago
• eclufsc / libertyParser
  Mirror of Synopsys's Liberty parser library
  ☆24Updated 7 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆52Updated last year
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆37Updated last year
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆52Updated 5 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆49Updated 4 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆57Updated 5 years ago
• hjking / uvm_gen
  UVM Generator
  ☆47Updated last year
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆151Updated 7 years ago
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆22Updated last year
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆77Updated 5 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆37Updated 5 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆50Updated 6 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆21Updated last year
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆72Updated 4 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆53Updated last year
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆37Updated 9 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆97Updated last year
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆64Updated 2 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆149Updated 5 months ago