Alternatives and similar repositories for skywater-pdk

Users that are interested in skywater-pdk are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenLane
  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…
  ☆1,555Updated last month
• The-OpenROAD-Project / OpenROAD
  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
  ☆2,110Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,061Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,491Updated this week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,831Updated this week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆558Updated this week
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,985Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,030Updated this week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,452Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆981Updated this week
• google / xls
  XLS: Accelerated HW Synthesis
  ☆1,332Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,131Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,627Updated 2 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆934Updated last month
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,058Updated this week
• google / gf180mcu-pdk
  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
  ☆414Updated 2 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,930Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,618Updated last year
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆818Updated 2 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,842Updated last month
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,095Updated 5 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,609Updated last week
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,375Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,444Updated last week
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,194Updated last year
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,840Updated this week
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆588Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,132Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,607Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆889Updated 2 years ago