google / skywater-pdkLinks
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
☆3,249Updated 10 months ago
Alternatives and similar repositories for skywater-pdk
Users that are interested in skywater-pdk are comparing it to the libraries listed below
Sorting:
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,565Updated last month
- Yosys Open SYnthesis Suite☆4,010Updated this week
- Modular hardware build system☆1,068Updated this week
- nextpnr portable FPGA place and route tool☆1,503Updated this week
- SERV - The SErial RISC-V CPU☆1,637Updated 3 months ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,844Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,861Updated 2 months ago
- An open-source static random access memory (SRAM) compiler.☆939Updated 2 months ago
- A small, light weight, RISC CPU soft core☆1,454Updated 3 weeks ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,144Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,098Updated 6 months ago
- Verilator open-source SystemVerilog simulator and lint system☆3,048Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,139Updated this week
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,131Updated this week
- Magic VLSI Layout Tool☆562Updated last week
- Build your hardware, easily!☆3,469Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,646Updated last year
- Universal utility for programming FPGA☆1,400Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,626Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,394Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,605Updated last week
- Documenting the Xilinx 7-series bit-stream format.☆824Updated 3 months ago
- Icarus Verilog☆3,136Updated this week
- An Open-source FPGA IP Generator☆990Updated this week
- A modern hardware definition language and toolchain based on Python☆1,768Updated last month
- cocotb: Python-based chip (RTL) verification☆2,074Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆597Updated this week
- Send video/audio over HDMI on an FPGA☆1,198Updated last year
- Scala based HDL☆1,843Updated this week
- VeeR EH1 core☆894Updated 2 years ago