Alternatives and similar repositories for skywater-pdk

Users that are interested in skywater-pdk are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenLane
  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…
  ☆1,637Updated 2 months ago
• The-OpenROAD-Project / OpenROAD
  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
  ☆2,280Updated last week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,619Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,554Updated last week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆588Updated this week
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,151Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,108Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,695Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,686Updated last week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,918Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆966Updated last month
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,697Updated this week
• google / gf180mcu-pdk
  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
  ☆441Updated 2 years ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,022Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,250Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,920Updated last month
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,846Updated last month
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,173Updated last week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,444Updated 4 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,363Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,800Updated last year
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,161Updated this week
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,127Updated last month
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,183Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆912Updated 2 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,480Updated 3 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,044Updated last week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,474Updated 3 weeks ago
• FPGAwars / icestudio
  Visual editor for open FPGA boards
  ☆1,840Updated 3 months ago
• vortexgpgpu / vortex
  ☆1,773Updated last week