google / skywater-pdkLinks
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
☆3,410Updated last year
Alternatives and similar repositories for skywater-pdk
Users that are interested in skywater-pdk are comparing it to the libraries listed below
Sorting:
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,695Updated 4 months ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,414Updated this week
- Modular hardware build system☆1,127Updated last week
- An open-source static random access memory (SRAM) compiler.☆1,002Updated 3 weeks ago
- Verilator open-source SystemVerilog simulator and lint system☆3,342Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,196Updated this week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,977Updated this week
- nextpnr portable FPGA place and route tool☆1,604Updated last week
- SERV - The SErial RISC-V CPU☆1,746Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,351Updated this week
- Magic VLSI Layout Tool☆613Updated this week
- cocotb: Python-based chip (RTL) verification☆2,251Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,764Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,797Updated this week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆463Updated 2 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,008Updated last month
- Build your hardware, easily!☆3,722Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,762Updated last month
- Yosys Open SYnthesis Suite☆4,272Updated this week
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆762Updated 2 weeks ago
- OpenTitan: Open source silicon root of trust☆3,125Updated last week
- A small, light weight, RISC CPU soft core☆1,507Updated 2 months ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,149Updated last month
- An Open-source FPGA IP Generator☆1,047Updated this week
- A modern hardware definition language and toolchain based on Python☆1,906Updated 2 weeks ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆674Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,133Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,485Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,072Updated last week
- RISC-V Cores, SoC platforms and SoCs☆909Updated 4 years ago