This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
☆34Jul 25, 2023Updated 2 years ago
Alternatives and similar repositories for sky130_cds
Users that are interested in sky130_cds are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆39Jun 2, 2021Updated 5 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Nov 13, 2020Updated 5 years ago
- Efabless mpw7 submission☆15May 6, 2024Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆63Mar 13, 2025Updated last year
- Tiny Tapeout project build tools + chip integration scripts☆34Jun 15, 2026Updated 3 weeks ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- PROTON - A Python Framework for Physics-Based Electromigration Assessment on Contemporary VLSI Power Grids☆19Sep 10, 2024Updated last year
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆32Jul 30, 2022Updated 3 years ago
- IO and periphery cells for SKY130 provided by SkyWater.☆14Nov 29, 2023Updated 2 years ago
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆14Apr 14, 2026Updated 2 months ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Jul 5, 2021Updated 5 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 2 months ago
- An open source PDK using TIGFET 10nm devices.☆60Dec 19, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆29Jan 14, 2026Updated 5 months ago
- Custom 6502 Video Game Console☆14May 8, 2026Updated 2 months ago
- ☆36Aug 23, 2022Updated 3 years ago
- Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects☆43May 26, 2026Updated last month
- React Component for Viewing Electronics Schematics☆20Jun 30, 2026Updated last week
- Reinforcement learning assisted analog layout design flow.☆38Jul 29, 2024Updated last year
- ☆17Oct 13, 2024Updated last year
- cadence flow for genus and innovus with UPF added.☆16Jul 3, 2021Updated 5 years ago
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- gnucap mirror (read only)☆34Jun 30, 2026Updated last week
- TinyQV - Crowdsourced Risc-V SoC☆37Jun 29, 2026Updated last week
- An innovative Verilog-A compiler - reloaded☆43Jun 19, 2026Updated 2 weeks ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆91Jun 12, 2023Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- Reproducing Gaussian Splatting☆15Jan 25, 2024Updated 2 years ago
- Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each…☆53Updated this week
- Active Learning Interface for Circuits and Electronics☆20Feb 18, 2023Updated 3 years ago
- ☆45Feb 25, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆92Mar 19, 2026Updated 3 months ago
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- SPAD Simulation☆10Jul 18, 2023Updated 2 years ago
- ☆12Jun 9, 2022Updated 4 years ago
- ☆11Nov 17, 2025Updated 7 months ago
- Design of BandGapReference Circuit using Sky130 PDK☆11Oct 30, 2021Updated 4 years ago
- Simulation engine for EEcircuit☆14Apr 5, 2026Updated 3 months ago