stineje / sky130_cds
This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
☆23Updated last year
Alternatives and similar repositories for sky130_cds:
Users that are interested in sky130_cds are comparing it to the libraries listed below
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆39Updated last month
- ☆40Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- ☆45Updated 2 months ago
- ☆16Updated 2 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆27Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated last month
- repository for a bandgap voltage reference in SKY130 technology☆37Updated 2 years ago
- ☆12Updated 2 years ago
- ☆20Updated 3 years ago
- Characterizer☆22Updated 7 months ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆59Updated 2 weeks ago
- ☆36Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆16Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- An automatic clock gating utility☆46Updated this week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆66Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆40Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- ☆31Updated 3 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- ☆43Updated 5 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 2 months ago