OSCC-Project / iMap
Logic optimization and technology mapping tool.
☆18Updated last year
Alternatives and similar repositories for iMap:
Users that are interested in iMap are comparing it to the libraries listed below
- Research paper based on or related to ABC.☆24Updated 2 weeks ago
- ☆14Updated 2 years ago
- ☆23Updated 9 months ago
- ☆21Updated 7 months ago
- Collection of digital hardware modules & projects (benchmarks)☆37Updated 2 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆39Updated 4 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆41Updated 2 weeks ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆21Updated 3 weeks ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated last month
- This is a python repo for flattening Verilog☆15Updated 3 weeks ago
- ☆14Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆24Updated 5 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆48Updated 3 weeks ago
- ☆28Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆16Updated 4 months ago
- Benchmarks for Approximate Circuit Synthesis☆15Updated 4 years ago
- ☆12Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆30Updated last week
- GPU-based logic synthesis tool☆79Updated 6 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆16Updated 4 years ago
- ☆16Updated 2 years ago
- ☆14Updated last year
- This is a repo to store circuit design datasets☆15Updated last year
- SMT-based-STDCELL-Layout-Generator☆16Updated 3 years ago
- ☆26Updated 8 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆12Updated 3 years ago
- ☆14Updated 2 months ago
- ☆12Updated last year
- ☆38Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 6 months ago