OSCC-Project / iMapLinks
Logic optimization and technology mapping tool.
☆20Updated 2 years ago
Alternatives and similar repositories for iMap
Users that are interested in iMap are comparing it to the libraries listed below
Sorting:
- Research paper based on or related to ABC.☆62Updated last month
- ☆18Updated 4 years ago
- ☆26Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆74Updated last week
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆40Updated last year
- ☆29Updated last year
- GPU-based logic synthesis tool☆97Updated 2 weeks ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- ☆20Updated 3 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆59Updated 11 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆29Updated 5 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆39Updated 5 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 8 months ago
- A logic synthesis tool☆82Updated 3 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Updated 3 years ago
- A high-efficiency hybrid solving CEC algorithm☆14Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆55Updated 11 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆44Updated last year
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- ☆31Updated 2 years ago
- Fast Symbolic Repair of Hardware Design Code☆32Updated 10 months ago
- ☆41Updated last year
- This is a python repo for flattening Verilog☆20Updated 7 months ago
- ☆77Updated 6 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆20Updated 11 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆38Updated 4 months ago
- ☆12Updated 2 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆34Updated 8 months ago
- ☆54Updated 6 months ago