OSCC-Project / iMapLinks
Logic optimization and technology mapping tool.
☆20Updated 2 years ago
Alternatives and similar repositories for iMap
Users that are interested in iMap are comparing it to the libraries listed below
Sorting:
- ☆18Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆71Updated 3 weeks ago
- Research paper based on or related to ABC.☆61Updated 3 weeks ago
- ☆26Updated last year
- ☆28Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆44Updated last year
- ☆20Updated 3 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 6 months ago
- This is a python repo for flattening Verilog☆20Updated 6 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆39Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆55Updated 10 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- GPU-based logic synthesis tool☆97Updated last week
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆38Updated 4 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆58Updated 10 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆20Updated 11 months ago
- Fast Symbolic Repair of Hardware Design Code☆28Updated 10 months ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- ☆41Updated last year
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Updated 3 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆29Updated 5 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 7 months ago
- ☆77Updated 5 months ago
- A logic synthesis tool☆82Updated 2 months ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated last year
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- ☆16Updated 2 years ago
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆38Updated 3 months ago