Alternatives and similar repositories for ventus-gpgpu-verilog

Users that are interested in ventus-gpgpu-verilog are comparing it to the libraries listed below

• RV-BOSC / OpenNoC
  ☆206Updated 4 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆107Updated 5 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆180Updated 2 months ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆176Updated 5 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆204Updated 5 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆155Updated 9 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆239Updated this week
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆162Updated 6 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆45Updated 3 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆26Updated 2 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆170Updated 3 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆155Updated 8 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆221Updated last week
• pulp-platform / fpu
  ☆57Updated 6 years ago
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆35Updated last year
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆76Updated this week
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆134Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆130Updated 5 years ago
• pulp-platform / ITA
  ☆55Updated 6 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆120Updated 5 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆138Updated 6 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆82Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆37Updated 4 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆299Updated last year
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆317Updated last month
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• OSCPU / ysyxSoC
  ☆89Updated last month
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆31Updated 3 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆195Updated 7 years ago