THU-DSP-LAB / ventus-gpgpu-doc
documentation for ventus gpgpu
☆15Updated last year
Alternatives and similar repositories for ventus-gpgpu-doc:
Users that are interested in ventus-gpgpu-doc are comparing it to the libraries listed below
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆22Updated 6 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆40Updated this week
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- Learn NVDLA by SOMNIA☆30Updated 5 years ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆40Updated this week
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year
- ☆42Updated 5 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆83Updated 6 months ago
- ☆30Updated last year
- 记录阅读各类paper的想法笔记(关注体系结构,机器学习系统,深度学习,计算机视觉)☆24Updated 5 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆124Updated this week
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- ☆40Updated 5 years ago
- gem5 FS模式实验手册☆33Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- ☆25Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆22Updated 3 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆83Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆34Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- HLS for Networks-on-Chip☆33Updated 3 years ago
- ☆89Updated last year
- ☆25Updated 4 months ago