Jerc007 / Open-GPGPU-FlexGrip-
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
☆97Updated last year
Alternatives and similar repositories for Open-GPGPU-FlexGrip-:
Users that are interested in Open-GPGPU-FlexGrip- are comparing it to the libraries listed below
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- RISC-V Matrix Specification☆21Updated 4 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- The multi-core cluster of a PULP system.☆89Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- ☆43Updated 6 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆38Updated last year
- ☆55Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆103Updated last week
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆70Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆89Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆106Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated 3 weeks ago
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated last week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆52Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated 2 weeks ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆65Updated last year
- ☆91Updated last year
- ☆41Updated 3 weeks ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆35Updated 3 years ago
- ☆34Updated 9 months ago
- Pure digital components of a UCIe controller☆59Updated last week
- ☆40Updated 4 months ago