StanfordAHA / lake
Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
☆20Updated this week
Alternatives and similar repositories for lake:
Users that are interested in lake are comparing it to the libraries listed below
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 4 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- ☆52Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- Stencil with Optimized Dataflow Architecture☆15Updated 10 months ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆29Updated last month
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- Floating point modules for CHISEL☆30Updated 10 years ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- DASS HLS Compiler☆27Updated last year
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- A Hardware Pipeline Description Language☆44Updated last year
- A configurable SRAM generator☆42Updated last week
- A polyhedral compiler for hardware accelerators☆55Updated 5 months ago
- Benchmarks for Yosys development☆23Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 4 months ago
- The specification for the FIRRTL language☆49Updated last week
- ☆15Updated 3 years ago