Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
☆24Mar 23, 2026Updated this week
Alternatives and similar repositories for lake
Users that are interested in lake are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆62Updated this week
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- Next generation CGRA generator☆119Mar 20, 2026Updated last week
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated last year
- ☆11Sep 14, 2020Updated 5 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- ☆82Feb 7, 2025Updated last year
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- Artifact associated with CHES 2022 paper https://tches.iacr.org/index.php/TCHES/article/view/9817☆12Nov 10, 2023Updated 2 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- ☆14May 23, 2024Updated last year
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- HLS branch of Halide☆79Jul 6, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- ☆14Aug 27, 2020Updated 5 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆186Mar 8, 2026Updated 2 weeks ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Dec 5, 2023Updated 2 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Mar 11, 2024Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Apr 30, 2019Updated 6 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- ☆105Jun 27, 2022Updated 3 years ago
- ☆16Jun 13, 2021Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Jun 11, 2024Updated last year
- Verilog code for a low power RFID chip that will communicate with I2C sensors.☆13Apr 18, 2014Updated 11 years ago
- A configurable SRAM generator☆58Mar 4, 2026Updated 3 weeks ago
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 10 months ago
- ☆29Nov 5, 2021Updated 4 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Nov 15, 2022Updated 3 years ago
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆29Feb 4, 2017Updated 9 years ago
- A lightweight, Pythonic, frontend for MLIR☆80Oct 21, 2023Updated 2 years ago
- HeteroCL-MLIR dialect for accelerator design☆42Sep 18, 2024Updated last year
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆15Mar 19, 2026Updated last week
- C++ Header-Only Library for High-Performance Tensor-Vector Multiplication☆23Nov 2, 2025Updated 4 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- Open-source AI acceleration on FPGA: from ONNX to RTL☆52Updated this week
- 21st century electronic design automation tools, written in Rust.☆36Mar 17, 2026Updated last week
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Mar 29, 2021Updated 4 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated 2 months ago