StanfordAHA / lakeLinks
Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
☆23Updated this week
Alternatives and similar repositories for lake
Users that are interested in lake are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 6 months ago
- A configurable SRAM generator☆57Updated 3 months ago
- Next generation CGRA generator☆116Updated this week
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆29Updated 3 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆52Updated 2 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- The OpenPiton Platform☆17Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated last month
- OpenDesign Flow Database☆16Updated 7 years ago
- ☆20Updated last year
- ☆44Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago