jingpu / Halide-HLSLinks
HLS branch of Halide
☆77Updated 7 years ago
Alternatives and similar repositories for Halide-HLS
Users that are interested in Halide-HLS are comparing it to the libraries listed below
Sorting:
- ☆81Updated 5 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- MAERI public release☆31Updated 3 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Updated 6 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆162Updated 3 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Updated 6 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆177Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆140Updated 5 years ago
- ☆88Updated 2 years ago
- MAESTRO binary release☆22Updated 5 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- CGRA Compilation Framework☆84Updated 2 years ago
- ☆28Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆92Updated last year
- ☆30Updated 6 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆76Updated 6 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆213Updated 5 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Next generation CGRA generator☆112Updated this week
- Fast and accurate DRAM power and energy estimation tool☆168Updated last week
- ☆24Updated 4 years ago
- Falcon Merlin Compiler☆41Updated 5 years ago