Alternatives and similar repositories for Halide-HLS

Users that are interested in Halide-HLS are comparing it to the libraries listed below

• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆64Updated 5 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated 3 months ago
• hipacc / hipacc-fpga
  Fork of Hipacc generating code for Vivado HLS and Altera OpenCL
  ☆24Updated 6 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆122Updated 5 years ago
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• KastnerRG / spector
  Spector: An OpenCL FPGA Benchmark Suite
  ☆48Updated 6 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆165Updated last year
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆71Updated 6 years ago
• sfu-arch / muir
  ☆24Updated 4 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆50Updated 6 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆57Updated 10 months ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• tukl-msd / LSTM-PYNQ
  ☆29Updated 7 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆91Updated 8 months ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆20Updated 8 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 11 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆83Updated last year
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆87Updated 2 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago