jingpu / Halide-HLS
HLS branch of Halide
☆77Updated 6 years ago
Alternatives and similar repositories for Halide-HLS:
Users that are interested in Halide-HLS are comparing it to the libraries listed below
- ☆80Updated 2 weeks ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Updated 6 years ago
- MAERI public release☆31Updated 3 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- ☆85Updated 2 years ago
- MAESTRO binary release☆22Updated 5 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆117Updated 4 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆61Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆67Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆132Updated 5 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- A polyhedral compiler for hardware accelerators☆55Updated 6 months ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- ☆71Updated 2 years ago
- ☆27Updated 5 years ago
- ☆90Updated last year
- ☆23Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 4 months ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- ☆29Updated 6 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆161Updated 3 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆19Updated 7 years ago