NVlabs / matchlibLinks
SystemC/C++ library of commonly-used hardware functions and components for HLS.
☆290Updated 2 months ago
Alternatives and similar repositories for matchlib
Users that are interested in matchlib are comparing it to the libraries listed below
Sorting:
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆328Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆223Updated 2 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆398Updated 2 months ago
- Build Customized FPGA Implementations for Vivado☆352Updated this week
- Network on Chip Simulator☆299Updated 2 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆333Updated 11 months ago
- SystemC/TLM-2.0 Co-simulation framework☆263Updated 7 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated last month
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆257Updated 3 weeks ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆145Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆309Updated 3 months ago
- PandA-bambu public repository☆304Updated this week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆125Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated last week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆165Updated 2 years ago
- ☆87Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated this week
- OpenSoC Fabric - A Network-On-Chip Generator☆175Updated 5 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆255Updated 3 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆299Updated this week
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- Next generation CGRA generator☆118Updated last week
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago