NVlabs / matchlibLinks
SystemC/C++ library of commonly-used hardware functions and components for HLS.
☆281Updated 4 months ago
Alternatives and similar repositories for matchlib
Users that are interested in matchlib are comparing it to the libraries listed below
Sorting:
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆302Updated 4 months ago
- A Chisel RTL generator for network-on-chip interconnects☆209Updated 3 weeks ago
- SystemC/TLM-2.0 Co-simulation framework☆255Updated 3 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- Network on Chip Simulator☆288Updated last month
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 11 months ago
- Build Customized FPGA Implementations for Vivado☆337Updated last week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆383Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆291Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆224Updated last month
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆324Updated 7 months ago
- PandA-bambu public repository☆278Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆263Updated last week
- Vitis HLS LLVM source code and examples☆395Updated 11 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆265Updated 2 weeks ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆283Updated 3 weeks ago
- ☆341Updated last year
- A dynamic verification library for Chisel.☆155Updated 10 months ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 9 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆158Updated 2 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆114Updated this week
- Code used in☆194Updated 8 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- Verilog Configurable Cache☆181Updated 9 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆223Updated 2 years ago
- Next generation CGRA generator☆114Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year