StanfordAHA / CGRAFlow
Integration test for entire CGRA flow
☆12Updated 5 years ago
Alternatives and similar repositories for CGRAFlow:
Users that are interested in CGRAFlow are comparing it to the libraries listed below
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- DASS HLS Compiler☆27Updated last year
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- A polyhedral compiler for hardware accelerators☆55Updated 6 months ago
- ☆16Updated 6 years ago
- Stencil with Optimized Dataflow Architecture☆15Updated 11 months ago
- ☆24Updated 5 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆25Updated 9 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆34Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 4 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 2 months ago
- ☆27Updated 5 years ago
- ☆15Updated last year
- CNN accelerator☆27Updated 7 years ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- FPU Generator☆20Updated 3 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆17Updated 8 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- ☆32Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- ☆40Updated 5 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago