StanfordAHA / CGRAFlowLinks
Integration test for entire CGRA flow
☆12Updated 5 years ago
Alternatives and similar repositories for CGRAFlow
Users that are interested in CGRAFlow are comparing it to the libraries listed below
Sorting:
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- ☆16Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 weeks ago
- OpenDesign Flow Database☆16Updated 6 years ago
- FPU Generator☆20Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Updated last year
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- CNN accelerator☆27Updated 8 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- A configurable SRAM generator☆56Updated last month
- Project repo for the POSH on-chip network generator☆50Updated 6 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- ☆44Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- ☆27Updated 5 years ago
- Next generation CGRA generator☆114Updated last week
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 9 years ago
- ☆26Updated 4 years ago
- ☆27Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago