StanfordAHA / CGRAFlowLinks
Integration test for entire CGRA flow
☆12Updated 5 years ago
Alternatives and similar repositories for CGRAFlow
Users that are interested in CGRAFlow are comparing it to the libraries listed below
Sorting:
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated this week
- FPU Generator☆20Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- ☆16Updated 7 years ago
- OpenDesign Flow Database☆17Updated 7 years ago
- CNN accelerator☆27Updated 8 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Updated 2 years ago
- Next generation CGRA generator☆118Updated this week
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- Stencil with Optimized Dataflow Architecture☆17Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆15Updated 3 years ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Updated last year
- ☆27Updated 4 years ago
- Fast PnR toolchain for CGRA☆19Updated last year
- ☆20Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- Matrix Multiply and Accumulate unit written in System Verilog☆12Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago