StanfordAHA / CGRAFlowLinks
Integration test for entire CGRA flow
☆12Updated 6 years ago
Alternatives and similar repositories for CGRAFlow
Users that are interested in CGRAFlow are comparing it to the libraries listed below
Sorting:
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ☆16Updated 7 years ago
- OpenDesign Flow Database☆17Updated 7 years ago
- CNN accelerator☆29Updated 8 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated 3 weeks ago
- FPU Generator☆20Updated 4 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 6 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Next generation CGRA generator☆118Updated last week
- ☆44Updated 6 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Updated last year
- An open source PDK using TIGFET 10nm devices.☆56Updated 3 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- ☆29Updated 6 years ago
- AMC: Asynchronous Memory Compiler☆52Updated 5 years ago
- ☆27Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Updated 2 years ago
- Open Source PHY v2☆33Updated last year
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆51Updated 5 years ago