StanfordAHA / CGRAFlowLinks
Integration test for entire CGRA flow
☆12Updated 5 years ago
Alternatives and similar repositories for CGRAFlow
Users that are interested in CGRAFlow are comparing it to the libraries listed below
Sorting:
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- DASS HLS Compiler☆29Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆16Updated 7 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- ☆44Updated 5 years ago
- ☆33Updated 5 years ago
- ☆27Updated 7 years ago
- Stencil with Optimized Dataflow Architecture☆16Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 weeks ago
- ☆27Updated 5 years ago
- Mirror of Synopsys's Liberty parser library☆22Updated 6 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated this week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- Fast PnR toolchain for CGRA☆18Updated 11 months ago
- ☆15Updated 2 years ago
- ☆29Updated 6 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆39Updated last month
- CNN accelerator☆27Updated 8 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago