rdaly525 / CS448HLinks
Github for CS448H Winter 2017
☆14Updated 7 years ago
Alternatives and similar repositories for CS448H
Users that are interested in CS448H are comparing it to the libraries listed below
Sorting:
- Integration test for entire CGRA flow☆12Updated 5 years ago
- High quality and composable RTL libraries in SystemVerilog☆25Updated this week
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated last year
- A polyhedral compiler for hardware accelerators☆59Updated 11 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Python wrapper for verilator model☆86Updated last year
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- ☆103Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 11 months ago
- Stencil with Optimized Dataflow Architecture☆16Updated last year
- The PE for the second generation CGRA (garnet).☆17Updated 2 months ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- Debuggable hardware generator☆69Updated 2 years ago
- Hierarchical Asynchronous Circuit Kompiler Toolkit☆24Updated 3 months ago
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆21Updated 5 years ago
- mantle library☆44Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Updated 6 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- ☆16Updated 7 years ago
- Verification Utilities for MyHDL☆17Updated last year
- Hardware generator debugger☆74Updated last year
- Next generation CGRA generator☆112Updated this week
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year