Dual-issue RV64IM processor for fun & learning
☆65Jul 4, 2023Updated 3 years ago
Alternatives and similar repositories for RISu064
Users that are interested in RISu064 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- Tightly Coupled Bus, low complexity, high performance system bus.☆13Apr 16, 2026Updated 6 months ago
- ☆20Dec 23, 2020Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆33Nov 25, 2022Updated 3 years ago
- ☆12Dec 22, 2020Updated 5 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated last month
- 64-bit multicore Linux-capable RISC-V processor☆124Apr 28, 2025Updated last year
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆107Jun 24, 2025Updated last year
- ☆40Nov 14, 2024Updated last year
- Demo SoC for SiliconCompiler.☆64Jul 2, 2026Updated 4 months ago
- ☆38Dec 29, 2022Updated 3 years ago
- RISC-V BSV Specification☆24Apr 28, 2026Updated 6 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A configurable SRAM generator☆72Oct 20, 2026Updated last week
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- Simple RISC-V processor for FPGAs☆21Apr 18, 2023Updated 3 years ago
- Riegel Computer☆17Jun 30, 2023Updated 3 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Oct 24, 2026Updated last week
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- ☆102Jul 22, 2026Updated 3 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- RISC-V microcontroller IP for embedded, FPGA and ASIC applications☆203Oct 16, 2026Updated 2 weeks ago
- ☆328Jan 23, 2026Updated 9 months ago
- ☆32Feb 4, 2021Updated 5 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 5 years ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆231Feb 19, 2026Updated 8 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆124Updated this week
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- PSOC SoC code with peripherals and synthesis scripts for FPGA/ASIC☆12Oct 8, 2025Updated last year
- RISC-V System on Chip Template☆162Aug 26, 2026Updated 2 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆15Jan 15, 2024Updated 2 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Oct 25, 2026Updated last week
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Updated this week
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆229Jun 5, 2026Updated 4 months ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 6 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 4 years ago