zephray / RISu064
Dual-issue RV64IM processor for fun & learning
☆57Updated last year
Alternatives and similar repositories for RISu064:
Users that are interested in RISu064 are comparing it to the libraries listed below
- Naive Educational RISC V processor☆79Updated 5 months ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- ☆33Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- SoftCPU/SoC engine-V☆54Updated last year
- Reusable Verilog 2005 components for FPGA designs☆40Updated 3 weeks ago
- A pipelined RISC-V processor☆51Updated last year
- LunaPnR is a place and router for integrated circuits☆46Updated 3 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆38Updated 2 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- RISC-V Nox core☆62Updated 7 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆78Updated this week
- PicoRV☆44Updated 5 years ago
- ☆36Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 10 months ago
- An implementation of RISC-V☆25Updated this week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆44Updated last year
- ☆59Updated 3 years ago
- Optimized RISC-V FP emulation for 32-bit processors☆31Updated 3 years ago
- A simple three-stage RISC-V CPU☆22Updated 3 years ago
- Wishbone interconnect utilities☆39Updated last month
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 4 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- An automatic clock gating utility☆44Updated 7 months ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago