Dual-issue RV64IM processor for fun & learning
☆64Jul 4, 2023Updated 2 years ago
Alternatives and similar repositories for RISu064
Users that are interested in RISu064 are comparing it to the libraries listed below
Sorting:
- RISC-V processor☆32May 26, 2022Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- A configurable SRAM generator☆58Aug 19, 2025Updated 6 months ago
- ☆33Nov 25, 2022Updated 3 years ago
- ☆38Dec 29, 2022Updated 3 years ago
- ☆22Jun 23, 2024Updated last year
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Feb 25, 2026Updated last week
- Demo SoC for SiliconCompiler.☆62Jan 28, 2026Updated last month
- ☆12Dec 22, 2020Updated 5 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Updated this week
- RISC-V System on Chip Template☆160Aug 18, 2025Updated 6 months ago
- ☆20Dec 23, 2020Updated 5 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆24May 13, 2023Updated 2 years ago
- Simple RISC-V processor for FPGAs☆21Apr 18, 2023Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Feb 25, 2026Updated last week
- ☆15Jun 22, 2023Updated 2 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆192Updated this week
- Raw data collected about the SKY130 process technology.☆63May 7, 2023Updated 2 years ago
- A small Neural Network Processor for Edge devices.☆16Nov 22, 2022Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- ☆309Jan 23, 2026Updated last month
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆28Feb 21, 2019Updated 7 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43May 5, 2023Updated 2 years ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- Riegel Computer☆17Jun 30, 2023Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Jan 5, 2025Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆106Apr 28, 2025Updated 10 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Feb 3, 2026Updated last month
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Mar 31, 2018Updated 7 years ago
- ☆30Feb 4, 2021Updated 5 years ago
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆24May 30, 2024Updated last year
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago