Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
☆287Mar 26, 2022Updated 4 years ago
Alternatives and similar repositories for OpenSERDES
Users that are interested in OpenSERDES are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog RTL Design☆50Sep 4, 2021Updated 4 years ago
- ☆26Feb 22, 2024Updated 2 years ago
- tools regarding on analog modeling, validation, and generation☆23Apr 11, 2023Updated 3 years ago
- All digital PLL☆28Dec 19, 2017Updated 8 years ago
- LunaPnR is a place and router for integrated circuits☆48Feb 11, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 4 years ago
- Automatic generation of real number models from analog circuits☆48Apr 2, 2024Updated 2 years ago
- Open Source PHY v2☆36Apr 25, 2024Updated 2 years ago
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated last year
- Time to Digital Converter (TDC)☆36Dec 27, 2020Updated 5 years ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,816Mar 25, 2026Updated 2 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆336Oct 22, 2025Updated 7 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆72May 13, 2026Updated 3 weeks ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆746Jun 1, 2026Updated last week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- KiCad symbol library for sky130 and gf180mcu PDKs☆37Feb 14, 2024Updated 2 years ago
- ☆30Feb 4, 2021Updated 5 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆169Nov 10, 2025Updated 7 months ago
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆264Updated this week
- Open source process design kit for 28nm open process☆83Apr 23, 2024Updated 2 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆37Apr 9, 2026Updated 2 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆152Mar 17, 2023Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Open Analog Design Environment☆26May 19, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆39Jul 11, 2022Updated 3 years ago
- Python library for SerDes modelling☆91Jul 18, 2024Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆130Jul 22, 2021Updated 4 years ago
- An open-source static random access memory (SRAM) compiler.☆1,069May 15, 2026Updated 3 weeks ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆424Updated this week
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- Library of open source PDKs☆77Apr 13, 2026Updated last month
- StatOpt Tool in Python☆21Nov 7, 2023Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆58Dec 19, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆80Updated this week
- Verilog PCI express components☆1,608Apr 26, 2024Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆122Jul 31, 2021Updated 4 years ago
- Verilog hardware abstraction library☆53May 24, 2026Updated 2 weeks ago
- An Open-source FPGA IP Generator☆1,111Updated this week
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆41Jun 10, 2021Updated 5 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆215Oct 6, 2025Updated 8 months ago