SparcLab / OpenSERDESLinks
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
☆252Updated 3 years ago
Alternatives and similar repositories for OpenSERDES
Users that are interested in OpenSERDES are comparing it to the libraries listed below
Sorting:
- Fabric generator and CAD tools.☆197Updated this week
- Verilog digital signal processing components☆155Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆156Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated 3 weeks ago
- FuseSoC standard core library☆147Updated 3 months ago
- Arduino compatible Risc-V Based SOC☆156Updated last year
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆347Updated 6 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆109Updated 4 years ago
- ☆83Updated 2 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆263Updated 2 weeks ago
- A complete open-source design-for-testing (DFT) Solution☆164Updated 2 weeks ago
- Control and status register code generator toolchain☆143Updated 3 weeks ago
- Control and Status Register map generator for HDL projects☆127Updated 3 months ago
- ☆103Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆115Updated 3 weeks ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆163Updated 2 years ago
- ☆52Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- https://caravel-user-project.readthedocs.io☆217Updated 6 months ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆156Updated 6 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆157Updated last year
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 11 months ago
- Verilog UART☆180Updated 12 years ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆288Updated 2 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆312Updated 6 months ago
- 10Gb Ethernet Switch☆229Updated 4 months ago