Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
☆270Mar 26, 2022Updated 3 years ago
Alternatives and similar repositories for OpenSERDES
Users that are interested in OpenSERDES are comparing it to the libraries listed below
Sorting:
- Verilog RTL Design☆47Sep 4, 2021Updated 4 years ago
- ☆24Feb 22, 2024Updated 2 years ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated last month
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- Automatic generation of real number models from analog circuits☆48Apr 2, 2024Updated last year
- Open Source PHY v2☆33Apr 25, 2024Updated last year
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated 11 months ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,726Sep 15, 2025Updated 6 months ago
- Time to Digital Converter (TDC)☆36Dec 27, 2020Updated 5 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆70Nov 26, 2025Updated 3 months ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆694Updated this week
- Fully Open Source FASOC generators built on top of open-source EDA tools☆323Oct 22, 2025Updated 5 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆34Dec 25, 2025Updated 2 months ago
- KiCad symbol library for sky130 and gf180mcu PDKs☆34Feb 14, 2024Updated 2 years ago
- Open source process design kit for 28nm open process☆72Apr 23, 2024Updated last year
- ☆30Feb 4, 2021Updated 5 years ago
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆223Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Nov 10, 2025Updated 4 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Open Analog Design Environment☆25May 19, 2023Updated 2 years ago
- ☆38Jul 11, 2022Updated 3 years ago
- Library of open source PDKs☆68Mar 3, 2026Updated 2 weeks ago
- Python library for SerDes modelling☆85Jul 18, 2024Updated last year
- StatOpt Tool in Python☆16Nov 7, 2023Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆124Jul 22, 2021Updated 4 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆402Mar 5, 2026Updated 2 weeks ago
- An open-source static random access memory (SRAM) compiler.☆1,021Mar 12, 2026Updated last week
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆147Mar 17, 2023Updated 3 years ago
- All digital PLL☆28Dec 19, 2017Updated 8 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆72Mar 15, 2026Updated last week
- An open source PDK using TIGFET 10nm devices.☆56Dec 19, 2022Updated 3 years ago
- Verilog PCI express components☆1,553Apr 26, 2024Updated last year
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆121Jul 31, 2021Updated 4 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆40Jun 10, 2021Updated 4 years ago
- Verilog hardware abstraction library☆49Mar 13, 2026Updated last week
- An Open-source FPGA IP Generator☆1,062Updated this week
- Implementation of the PCIe physical layer☆61Jul 11, 2025Updated 8 months ago